Patents by Inventor Yoshiki Sano

Yoshiki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538845
    Abstract: Disclosed is a light receiving element including an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes a photodiode, a first transfer transistor that transfers electric charge generated in the photodiode to a first charge storage portion, a second transfer transistor that transfers electric charge generated in the photodiode to a second charge storage portion, and an interpixel separation portion that separates the semiconductor layers of adjacent pixels from each other, for at least part of the semiconductor layer in the depth direction. The wiring layer has at least one layer including a light blocking member. The light blocking member is disposed to overlap with the photodiode in a plan view.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: December 27, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiki Ebiko, Koji Neya, Takuya Sano
  • Patent number: 5801671
    Abstract: A liquid crystal display panel 51 of N rows.times.M columns is driven by a segment driver 52 with two different voltages VS1, VS2, and by a common driver 53 with three voltages VC1, VC2, VC3. An output voltage waveform of the segment driver 52 is modulated for gradation display. The two different voltages VS1, VS2 are selected to be low voltages so as not to require high withstand voltage process in the segment driver 52, which makes it easier to integrated to a large scale in the case of realizing the segment driver 52 as a semiconductor integrated circuit.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: September 1, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masakazu Kobayashi, Tatsuya Nakai, Hiroyuki Hirashima, Masahiko Monomohshi, Yoshiki Sano
  • Patent number: 5376926
    Abstract: A liquid crystal driver circuit is arranged to select one of a plurality of different reference voltages in response to externally input through the effect of a multiplexer circuit. The liquid crystal driver further provides a buffer circuit at an output stage of the multiplexer circuit, arranged in a manner that its impedance is high at an input and low at an output to thereby lower an output impedance of the liquid crystal driver circuit.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: December 27, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiki Sano
  • Patent number: 5311072
    Abstract: A sample/hold apparatus includes at least one sample/hold circuit. The at least one sample/hold circuit has a resistor connected to an input bus at one end thereof, a sampling gate connected to the other end of the resistor at one end thereof for opening and closing in response to a sampling signal supplied thereto, and a first capacitor connected to the other end of the sampling gate at one end thereof for holding analog data supplied from the input bus through the resistor and the sampling gate.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: May 10, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyohisa Matsui, Junji Tanaka, Yoshiki Sano
  • Patent number: 5296751
    Abstract: A sample-and-hold circuit includes two capacitors connected to an input signal line through respective analog switches for holding an input signal. An amplifier circuit of the sample-and-hold circuit includes two input terminals for receiving voltages held in the respective two capacitors and for amplifying the received voltages. The amplifier circuit alternately amplifies the voltages received through the two input terminals.
    Type: Grant
    Filed: March 23, 1992
    Date of Patent: March 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiki Sano
  • Patent number: 5289063
    Abstract: An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: February 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukihisa Orisaka, Junji Tanaka, Yoshiki Sano
  • Patent number: 5287405
    Abstract: A called party response detecting apparatus of a terminal equipment includes a plurality of filter units, a determining unit, and an analyzing unit. The filter units are commonly connected to an input side and detects specific frequency components included in a plurality of signal tones coming from a telephone line. The determining unit checks the presence/absence of each output from the filter units for each fundamental period to determine a signal type on the basis of a predetermined output pattern. The analyzing unit analyzes various signal tones and a called party response on the basis of occurrences of signal type outputs during a predetermined time period of the determining unit.
    Type: Grant
    Filed: January 2, 1991
    Date of Patent: February 15, 1994
    Assignee: Tamura Electric Works, Ltd.
    Inventor: Yoshiki Sano
  • Patent number: 5119267
    Abstract: A capacitor having a semiconductor substrate with a diffusion layer disposed in a portion of the semiconductor substrate and a first insulation layer disposed on the semiconductor substrate and the diffusion layer, the capacitor capable of providing a capacitance stably for an integrated circuit includes a first metallic layer disposed on the diffusion layer for conducting an electric current therethrough with the first insulation layer between the semiconductor substrate, a second insulation layer disposed on the first metallic layer for insulating the first metallic layer, and a second metallic layer disposed on the second insulation layer for conducting an electric current therethrough, the capacitance being expressed by C with a relation of C=C.sub.M +C.sub.B, the C.sub.M representing a capacitance occurred between the first metallic layer and the second metallic layer, the C.sub.B representing a capacitance occurred between the first metallic layer and the semiconductor substrate, respectively.
    Type: Grant
    Filed: August 24, 1990
    Date of Patent: June 2, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiki Sano, Yoshinori Ogawa
  • Patent number: 4811386
    Abstract: A called party response detecting apparatus includes a plurality of filter units for respectively detecting natural frequency components included in a plurality of signals sent from a telephone line. The apparatus also includes switching units for switching input levels of the filter units in a plurality of steps and a continuous signal detector for detecting that a logical sum output from the filter units has continued for a predetermined interval of time. An input level control unit operates to control the switching units to set an input level at a lowest level while waiting for a signal and also to reset the input level at a predetermined level different from the lowest level when an output is obtained from one of the filter units. During this reset operation, the input level control unit decreases the input level in steps until an output is obtained from the continuous signal detector.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: March 7, 1989
    Assignee: Tamura Electric Works, Ltd.
    Inventors: Yoshiki Sano, Masaaki Tsukada
  • Patent number: 4768223
    Abstract: A public telephone set that processes call charge information is provided. The set includes a register for holding a pre-determined number of digits of the dialed number and a memory in which dial control codes corresponding to the predetermined number of digits are stored in advance. Depending upon the telephone number that is dialed, a memory location is directly addressed to obtain a control code. The control code specifies a memory location in which charging information such as a charge or time increment is stored. This information is then processed to determine the appropriate charge for the number dialed.
    Type: Grant
    Filed: March 6, 1986
    Date of Patent: August 30, 1988
    Assignee: Tamura Electric Works, Ltd.
    Inventors: Toshiharu Kinoshita, Shuji Kunii, Yoshiki Sano