Patents by Inventor Yoshiki Yamamoto

Yoshiki Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369457
    Abstract: A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.
    Type: Application
    Filed: March 20, 2023
    Publication date: November 16, 2023
    Inventor: Yoshiki YAMAMOTO
  • Patent number: 11810926
    Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 7, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Publication number: 20230282647
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
  • Publication number: 20230253456
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Patent number: 11695012
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 4, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Patent number: 11658211
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: May 23, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Publication number: 20220157863
    Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 19, 2022
    Inventor: Yoshiki YAMAMOTO
  • Patent number: 11152393
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 19, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Publication number: 20210257459
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: April 7, 2021
    Publication date: August 19, 2021
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Publication number: 20210012892
    Abstract: Provided is a system that includes an electronic clinical record server configured to manage patient attributes and main medical information records, an information sharing server configured to manage accompanying medical information records which the electronic clinical record server does not manage, and a user terminal connected to the electronic clinical record server and the information sharing server via a network and configured to enable a staff member to enter and view the main and accompanying medical information records, and where the information sharing server is configured to integrate and manage the accompanying medical information records relating to the respective services as shared medical information records based on a prescribed format, and to provide the shared medical information records to the user terminal.
    Type: Application
    Filed: November 14, 2018
    Publication date: January 14, 2021
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kohei NAGURA, Yoshiki YAMAMOTO, Shuichi KASAI, Toshiki YAMAGUCHI, Mariko MURAKAMI
  • Publication number: 20200343268
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
  • Patent number: 10756115
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Publication number: 20200260366
    Abstract: Regarding display of browsing information on a portable terminal, it is possible to impose a browsing restriction on a person who does not have a browsing authorization with a simple configuration while avoiding a hindrance to easy access to the browsing information.
    Type: Application
    Filed: September 27, 2017
    Publication date: August 13, 2020
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshiki YAMAMOTO, Takashi MUKAIYAMA, Shingo TSUKIHARA, Yuji NAGAISHI, Koichi AIHARA
  • Publication number: 20200066757
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
  • Patent number: 10559595
    Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Publication number: 20200013857
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Patent number: 10529630
    Abstract: A substrate including an insulating layer, a semiconductor layer, and an insulating film stacked on a semiconductor substrate and having a trench filled with an element isolation portion is provided. After removal of the insulating film from a bulk region by a first dry etching, the semiconductor layer is removed from the bulk region by a second dry etching. Then, the insulating film in an SOI region and the insulating layer in the bulk region are removed. A gas containing a fluorocarbon gas is used for first dry etching. The etching thickness of the element isolation portion by a first dry etching is at least equal to the sum of the thicknesses of the insulating film just before starting the first dry etching and the semiconductor layer just before starting the first dry etching. After first dry etching and before second dry etching, oxygen plasma treatment is performed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Maruyama, Yoshiki Yamamoto, Toshiya Saitoh
  • Patent number: 10510775
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Publication number: 20190348439
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventor: Yoshiki Yamamoto
  • Patent number: 10461158
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura