Patents by Inventor Yoshiko Nagasaka
Yoshiko Nagasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11157821Abstract: A traceability system includes: a Equipment table that stores production data of a product manufactured in a first process, in which an individual ID is appended to a product; a Equipment table that stores production data of a product manufactured in a second process, in which an individual ID is not appended to a product; a training data setting unit that creates a training data table that stores the Equipment table and the Equipment table, which are correlated with each other; a feature amount extracting unit that calculates a cycle time of a predetermined number of products manufactured in the past in the first process; a model creation section that creates a production time estimation model for estimating a production time at which a product has been manufactured in the second process on the basis of the cycle time of the products; and a production time estimating unit.Type: GrantFiled: May 31, 2018Date of Patent: October 26, 2021Assignee: HITACHI, LTD.Inventors: Qi Xiu, Yoshiko Nagasaka, Keiro Muro, Hiromitsu Nakagawa
-
Patent number: 10789303Abstract: An information processing system includes: a document reception unit configured to receive multiple pieces of document data; a data storage unit configured to store the received multiple pieces of document data; and a correspondence relation estimation unit configured to estimate a correspondence relation at least between an item in a first document data and an item in a second document data out of the multiple pieces of document data stored in the data storage unit. The correspondence relation estimation unit includes an item-item coupling relation extraction unit configured to extract a coupling relation among items in the first document data and a coupling relation among items in the second document data, and a word relationship extraction unit configured to extract a relevance between a word that appears in an item in the first document data and a word that appears in an item in the second document data.Type: GrantFiled: March 23, 2018Date of Patent: September 29, 2020Assignee: HITACHI LTD.Inventors: Yoshiko Nagasaka, Keiro Muro
-
Publication number: 20190065491Abstract: An information processing system includes: a document reception unit configured to receive multiple pieces of document data; a data storage unit configured to store the received multiple pieces of document data; and a correspondence relation estimation unit configured to estimate a correspondence relation at least between an item in a first document data and an item in a second document data out of the multiple pieces of document data stored in the data storage unit. The correspondence relation estimation unit includes an item-item coupling relation extraction unit configured to extract a coupling relation among items in the first document data and a coupling relation among items in the second document data, and a word relationship extraction unit configured to extract a relevance between a word that appears in an item in the first document data and a word that appears in an item in the second document data.Type: ApplicationFiled: March 23, 2018Publication date: February 28, 2019Applicant: HITACHI, LTD.Inventors: Yoshiko NAGASAKA, Keiro MURO
-
Publication number: 20180349780Abstract: A traceability system includes: a Equipment table that stores production data of a product manufactured in a first process, in which an individual ID is appended to a product; a Equipment table that stores production data of a product manufactured in a second process, in which an individual ID is not appended to a product; a training data setting unit that creates a training data table that stores the Equipment table and the Equipment table, which are correlated with each other; a feature amount extracting unit that calculates a cycle time of a predetermined number of products manufactured in the past in the first process; a model creation section that creates a production time estimation model for estimating a production time at which a product has been manufactured in the second process on the basis of the cycle time of the products; and a production time estimating unit.Type: ApplicationFiled: May 31, 2018Publication date: December 6, 2018Inventors: Qi XIU, Yoshiko NAGASAKA, Keiro MURO, Hiromitsu NAKAGAWA
-
Publication number: 20160124841Abstract: The information processing apparatus includes a preprocessing unit that allocates the identifier to one or more collected groups, the main storage unit including a buffer having a size of the predetermined unit installed for each group, the storage unit that stores the data written in the buffer for each predetermined unit and each group, a write processing unit that acquires the data allocated to the group for each group and writes the acquired data in the buffer, determines whether or not the data of the predetermined unit has been written in the buffer, and causes the storage unit to store the data written in the buffer when the data of the predetermined unit is determined to have been written in the buffer, and a read processing unit that reads the stored data out to the main storage unit for each group, extracts the read data, and executes the process.Type: ApplicationFiled: June 6, 2013Publication date: May 5, 2016Applicant: HITACHI, LTD.Inventors: Takumi NITO, Yoshiko NAGASAKA, Hiroshi UCHIGAITO
-
Publication number: 20110161644Abstract: When a plurality of OSs are mounted, it is desirable to efficiently use memory resources without affecting other OSs. Also, even if the OSs are different from each other, they are mounted on one system, and therefore, inter-OS communication is required. In this case, data communication without affecting other OSs is required. Accordingly, an information processor includes: a firmware for assigning a first central processing unit, a first operating system, and a first region being a partial region of a memory as a first domain, assigning a second central processing unit, a second operating system, and a second region being a partial region of the memory as a second domain, and controlling to disable an access of one domain to a region assigned for the other domain; and a middleware for controlling a communication when the data communication is required between the first domain and the second domain.Type: ApplicationFiled: February 26, 2009Publication date: June 30, 2011Inventors: Tohru Nojiri, Keisuke Toyama, Yoshiko Nagasaka, Yuji Saeki
-
Publication number: 20100064070Abstract: In order to improve throughput by suppressing contention of hardware resources in a computer to which a data transfer unit is coupled, a control unit for transferring data between a first interface coupled to the computer and a second interface coupled to a memory transaction issuing unit for issuing, when one of the first interface and the second interface receives an access request to a memory of the computer, a memory transaction for the main memory to the first interface, the first interface includes a plurality of interfaces coupled in parallel to the computer, and the control unit further includes a memory transaction distribution unit for extracting an address of the main memory, which is contained in the memory transaction issued by the memory transaction issuing unit, and selecting an interface having address designation information set therein, which corresponds to the extracted address to transmit the memory transaction.Type: ApplicationFiled: August 24, 2009Publication date: March 11, 2010Inventors: Chihiro Yoshimura, Yoshiko Nagasaka, Naonobu Sukegawa, Koichi Takayama
-
Publication number: 20090016332Abstract: To exchange data between adjacent nodes at high speed while using an existing network including a fat tree and a multistage crossbar switch. This invention provides a parallel computer system including: a plurality of nodes each of which includes a processor and a communication unit; a switch for connecting the plurality of nodes with each other; a first network for connecting each of the plurality of nodes and the switch; and a second network for partially connecting the plurality of nodes with each other. Further, the first network is comprised of one of a fat tree and a multistage crossbar network. Further, the second network partially connects predetermined nodes among the plurality of nodes directly with each other.Type: ApplicationFiled: January 29, 2008Publication date: January 15, 2009Inventors: Hidetaka Aoki, Yoshiko Nagasaka