Yoshikuni Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A data processing system comprises: an instruction queue memory; an instruction decode unit; an address computation unit; an address translation unit; and an instruction execution unit. Further comprised is a decoded instruction queue memory having a queue structure composed of a plurality of entries for latching an entry information. The decoded instruction queue memory includes: a first counter adapted to be counted up in response to the effective address computation requiring signal of the instruction decode unit and down in response to the translation completion signal of the address translation unit; and a second counter having a counting-down function. When the first and second counters are to be counted down, one closer to the instruction execution unit and having a counted value other than zero is counted down. When the queue is the decoded instruction queue memory advances, the first counter has its counted value copied to that of the second counter and then set at the value of zero.
Abstract: An address generation system comprising a decoder for decoding an addressing field of a given instruction code, and a control circuit connected to the decoder to cause a register to be read out in accordance with the decoded information. A hold circuit is connected to the decoder to hold an address generation information for generating an address of an operand. A correction number generator is connected to the hold circuit to generate a correction number determined in accordance with the address generation information for the designated register. An adder is provided to receive the correction number and the content read out from the register and to output the content of the register modified by the correction number.
Abstract: An information processing apparatus having a jump operation function comprises a memory storing a first type instruction containing an operation code which designates an operation other than a jump operation and a control code which designates the jump operation and a second type instruction containing a jump address, a control circuit coupled to the memory and generating a control signal or signals to be used to execute the operation designated by the operation code and a jump operation signal according to the control code, and an addressing circuit coupled to the memory and the control circuit and applying the jump address contained in the second type instruction to the memory according to the jump operation signal generated at the same time when the control signal or signals are generated.
Abstract: A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device.