Abstract: A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

Abstract: A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

Abstract: In order to generate a constant voltage, a reference voltage is generated. Short wave noises are cut off from the reference voltage. A control signal is generated based on the reference voltage and an output voltage. The output voltage is controlled in response to the control signal to provide a constant output voltage.

Abstract: One semiconductor memory device according to the invention comprises a plurality of memory blocks, signal lines respectively connected to the plurality of memory blocks, and a control circuit connected to the signal lines, and the control circuit includes selection signal generator circuits for generating selection signals for selecting one memory block of the plurality of memory blocks by externally input address signals and for outputting the selection signals to the signal lines, and the lengths of the signal lines from the selection signal generator circuits to the respective memory blocks are longer in proportion to distances from the control circuit to the memory blocks. Thereby, parasitic load capacitances of the signal lines connected to the respective memory blocks in the wiring direction can be reduced, and the semiconductor memory device that operates with lower current consumption can be provided.

Abstract: A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

Abstract: One semiconductor memory device according to the invention comprises a plurality of memory blocks, signal lines respectively connected to the plurality of memory blocks, and a control circuit connected to the signal lines, and the control circuit includes selection signal generator circuits for generating selection signals for selecting one memory block of the plurality of memory blocks by externally input address signals and for outputting the selection signals to the signal lines, and the lengths of the signal lines from the selection signal generator circuits to the respective memory blocks are longer in proportion to distances from the control circuit to the memory blocks. Thereby, parasitic load capacitances of the signal lines connected to the respective memory blocks in the wiring direction can be reduced, and the semiconductor memory device that operates with lower current consumption can be provided.

Abstract: A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, a first wafer burn-in signal terminal, and a second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.

Abstract: A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, first wafer burn-in signal terminal, and second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.

Abstract: A semiconductor memory includes a memory array; data buses connected to the memory array; a plurality of data transmission circuits connected to the data buses one by one; and a buffer circuit connected to an outside device. The memory further includes a gate circuit arranged between the data transmission circuits and the buffer circuit; and a fuse connected to the gate circuit. The data transmission circuits are selectively connected to the buffer circuit by controlling the fuse and the gate circuit, so that a defective element is replaced with a normal element.

Abstract: An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.

Abstract: A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines.

Abstract: In a semiconductor memory device having memory cells (21.sub.i, 21.sub.i+1) disposed at intersections of bit lines (BL, BL) and word lines (WL.sub.i, WL.sub.i+1) and operating on an internal power source voltage (V.sub.D) which is lower than an external power source voltage for the memory device, sense amplifiers (41) are activated by a voltage on a drive common node (NS), and a comparator (110) is activated by the control signal (PAS) and compares the voltage on the common node (PS) with the internal power source voltage (V.sub.D). The comparator has an output which is in a first state when the common node (PS) voltage is not higher than the reference voltage (V.sub.R) and which is in a second state when the common node (PS) voltage exceeds the reference voltage (V.sub.R).

Abstract: In a dynamic random access memory comprising first and second memory cell arrays, and a plurality of word lines, each split into two sections extending through the first and the second memory cell arrays, respectively, word line drive circuits are divided into three blocks. The first block is disposed between the inner sides of the memory cell arrays and connected to the inner ends of the alternate word line sections. The second and the third blocks are disposed adjacent to the outer sides of the memory cell arrays and are connected to the outer ends of the intervening word line sections. Because the word line drive circuits for the respective word lines are disposed on both sides of each memory cell array, alternately, the area for the word line drive circuit for each word line can extend twice the pitch of the word lines. Thus, the pitch of the word lines can be reduced, or the size of the word line drive transistors can be increased, enabling a higher degree of integration.