Patents by Inventor Yoshimi Kohda

Yoshimi Kohda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6839872
    Abstract: A media converter allowing a test mode to be activated from cable side and allowing easy detection of a failure and failure location is disclosed. A media converter includes first and second physical-layer interfaces and a memory connected between the first and second physical-layer interfaces to temporarily storing received data. When a trigger signal has been received at one of the first and second physical-layer interfaces, a response signal to the trigger signal is sent from a corresponding physical-layer interface back to a source that transmitted the trigger signal. The trigger signal is one of a specified modulation link signal and a packet having an illegal length that is not permitted in a network to which the media converter belongs.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: January 4, 2005
    Assignee: Allied Telesis Kabushiki Kaisha
    Inventor: Yoshimi Kohda
  • Publication number: 20020178411
    Abstract: A media converter allowing a test mode to be activated from cable side and allowing easy detection of a failure and failure location is disclosed. A media converter includes first and second physical-layer interfaces and a memory connected between the first and second physical-layer interfaces to temporarily storing received data. When a trigger signal has been received at one of the first and second physical-layer interfaces, a response signal to the trigger signal is sent from a corresponding physical-layer interface back to a source that transmitted the trigger signal. The trigger signal is one of a specified modulation link signal and a packet having an illegal length that is not permitted in a network to which the media converter belongs.
    Type: Application
    Filed: September 7, 2001
    Publication date: November 28, 2002
    Inventor: Yoshimi Kohda
  • Patent number: 6420906
    Abstract: An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a forward direction. A second FET is connected between a corresponding input terminal and the output terminal in the same manner as the first FET. Each of the input voltages is compared with the output voltage. The conduction/non-conduction states of each of the first and second FETs are independently controlled depending on the comparison result.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 16, 2002
    Assignee: Allied Telesis Kabushiki Kaisha
    Inventor: Yoshimi Kohda
  • Publication number: 20020039034
    Abstract: An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a forward direction. A second FET is connected between a corresponding input terminal and the output terminal in the same manner as the first FET. Each of the input voltages is compared with the output voltage. The conduction/non-conduction states of each of the first and second FETs are independently controlled depending on the comparison result.
    Type: Application
    Filed: March 22, 2001
    Publication date: April 4, 2002
    Inventor: Yoshimi Kohda
  • Patent number: 5990577
    Abstract: A hub for a local area network according to one embodiment of the present invention includes a plurality of communication ports connected to each of nodes in the network, through which a signal is transmitted among the nodes, a signal processing circuit having at least the functions of repeating the signal among the nodes and reshaping a waveform thereof, and a power supply circuit for supplying a dc current for driving the signal processing circuit.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: November 23, 1999
    Assignee: Allied Telesis K. K.
    Inventors: Hideo Kamioka, Minoru Dendou, Yoshimi Kohda, Koji Kobayashi