Patents by Inventor Yoshimi Sudou

Yoshimi Sudou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7692234
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20090230453
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: September 27, 2007
    Publication date: September 17, 2009
    Inventors: Tetsuo ADACHI, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7528036
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: May 5, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7304345
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: December 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7195976
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7179711
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 20, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7141475
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: November 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20060051977
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: November 4, 2005
    Publication date: March 9, 2006
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20050189579
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: April 18, 2005
    Publication date: September 1, 2005
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20050098823
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: September 30, 2004
    Publication date: May 12, 2005
    Inventors: Tetsuo Adachi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20050090058
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 28, 2005
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20040253788
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: May 24, 2004
    Publication date: December 16, 2004
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20030148583
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 7, 2003
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20020192887
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: June 18, 2002
    Publication date: December 19, 2002
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 6461916
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 6444554
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 3, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Publication number: 20020064898
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Application
    Filed: December 11, 2001
    Publication date: May 30, 2002
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 6194763
    Abstract: To suppress floating substrate in the thin SOI.MOSFET formed on the SOI substrate, the gate (electrode) has a two-layer structure and the upper gate thereof is in contact with the sides of the SOI layer (substrate).
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Dai Hisamoto, Yoshimi Sudou
  • Patent number: 6060750
    Abstract: To suppress floating substrate in the thin SOI.MOSFET formed on the SOI substrate, the gate (electrode) has a two-layer structure and the upper gate thereof is in contact with the sides of the SOI layer (substrate).
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: May 9, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Dai Hisamoto, Yoshimi Sudou