Patents by Inventor Yoshimi Sudou
Yoshimi Sudou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7692234Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: September 27, 2007Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20090230453Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: September 27, 2007Publication date: September 17, 2009Inventors: Tetsuo ADACHI, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 7528036Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: April 18, 2005Date of Patent: May 5, 2009Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 7304345Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: November 4, 2005Date of Patent: December 4, 2007Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 7195976Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: May 24, 2004Date of Patent: March 27, 2007Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 7179711Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: September 30, 2004Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 7141475Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: September 30, 2004Date of Patent: November 28, 2006Assignee: Renesas Technology Corp.Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20060051977Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: November 4, 2005Publication date: March 9, 2006Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20050189579Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: April 18, 2005Publication date: September 1, 2005Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20050098823Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: September 30, 2004Publication date: May 12, 2005Inventors: Tetsuo Adachi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20050090058Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: September 30, 2004Publication date: April 28, 2005Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20040253788Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: May 24, 2004Publication date: December 16, 2004Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20030148583Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: February 27, 2003Publication date: August 7, 2003Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20020192887Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: June 18, 2002Publication date: December 19, 2002Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6461916Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: February 7, 2000Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6444554Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: December 11, 2001Date of Patent: September 3, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20020064898Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: December 11, 2001Publication date: May 30, 2002Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6194763Abstract: To suppress floating substrate in the thin SOI.MOSFET formed on the SOI substrate, the gate (electrode) has a two-layer structure and the upper gate thereof is in contact with the sides of the SOI layer (substrate).Type: GrantFiled: February 18, 2000Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Dai Hisamoto, Yoshimi Sudou
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Patent number: 6060750Abstract: To suppress floating substrate in the thin SOI.MOSFET formed on the SOI substrate, the gate (electrode) has a two-layer structure and the upper gate thereof is in contact with the sides of the SOI layer (substrate).Type: GrantFiled: December 29, 1997Date of Patent: May 9, 2000Assignee: Hitachi, Ltd.Inventors: Dai Hisamoto, Yoshimi Sudou