Patents by Inventor Yoshimichi Sogawa
Yoshimichi Sogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130291380Abstract: The present invention is: a package main body section having a hollow section; and an electronic device provided in the hollow section in the package main body section, in the package main body section, there being formed a through hole, through which the hollow section communicates with outside of the package main body section, and in the through hole, there being provided a sealing section in which a vicinity of the through hole is partly heated and a constituent material of the package main body section is melted to thereby block the through hole.Type: ApplicationFiled: July 2, 2013Publication date: November 7, 2013Applicant: NEC CORPORATIONInventors: TAKAO YAMAZAKI, MASAHIKO SANO, SEIJI KURASHIMA, YOSHIMICHI SOGAWA
-
Publication number: 20130234295Abstract: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a. 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c, 3d to extend through terminal pad 2a, semiconductor substrate 1, and terminal pad 2b. Insulating layer 4 made of SiO2, SiN, SiO, or the like is formed on the inner surfaces of throughholes 9. Buffer layer 5 made of a conductive adhesive is formed to cover insulating layer 4 and terminal pads 2a, 2b in openings 3c, 3d. Further, conductive layer 6 made of a metal film is formed on buffer layer 5 by electrolytic plating, non-electrolytic plating, or the like.Type: ApplicationFiled: April 16, 2013Publication date: September 12, 2013Applicants: RENESAS ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Yoshimichi Sogawa, Takao Yamazaki, Ichirou Hazeyama, Sakae Kitajou, Nobuaki Takahashi
-
Patent number: 8525323Abstract: The present invention is: a package main body section having a hollow section; and an electronic device provided in the hollow section in the package main body section, in the package main body section, there being formed a through hole, through which the hollow section communicates with outside of the package main body section, and in the through hole, there being provided a sealing section in which a vicinity of the through hole is partly heated and a constituent material of the package main body section is melted to thereby block the through hole.Type: GrantFiled: January 28, 2009Date of Patent: September 3, 2013Assignee: NEC CorporationInventors: Takao Yamazaki, Masahiko Sano, Seiji Kurashina, Yoshimichi Sogawa
-
Patent number: 8411450Abstract: The present invention is directed to provide a semiconductor package and the like realizing reduced manufacturing cost and improved reliability by enhancing a ground line and/or a power supply line. A semiconductor package 50 includes: a semiconductor device 1 including a circuit face on which an external electrode is formed; an insertion substrate 2 forming a housing part in which the semiconductor device 1 is disposed; and an interposer substrate 5 including a wiring pattern 7 and whose both ends are bent along the insertion substrate 2. The insertion substrate 2 is made of a conductive material and is electrically connected to a ground line or a power supply line in the wiring pattern 7 in the interposer substrate 5.Type: GrantFiled: January 25, 2007Date of Patent: April 2, 2013Assignee: NEC CorporationInventors: Takao Yamazaki, Yoshimichi Sogawa, Tomohiro Nishiyama
-
Publication number: 20110304029Abstract: A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 ?m, and the low-elasticity particles have a diameter of, e.g., 1 ?m. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.Type: ApplicationFiled: August 23, 2011Publication date: December 15, 2011Inventors: Yoshimichi Sogawa, Takao Yamazaki, Nobuaki Takahashi
-
Publication number: 20110114840Abstract: The present invention is: a package main body section having a hollow section; and an electronic device provided in the hollow section in the package main body section, in the package main body section, there being formed a through hole, through which the hollow section communicates with outside of the package main body section, and in the through hole, there being provided a sealing section in which a vicinity of the through hole is partly heated and a constituent material of the package main body section is melted to thereby block the through hole.Type: ApplicationFiled: January 28, 2009Publication date: May 19, 2011Inventors: Takao Yamazaki, Masahiko Sano, Seiji Kurashina, Yoshimichi Sogawa
-
Patent number: 7812440Abstract: There is provided an electronic device package and the like in which it is not likely that damage occurs in a wiring pattern of an interposer substrate in a gap section formed, for example, between an electronic device and an insertion substrate. The semiconductor package in accordance with the present invention is a package of fan-out type including an interposer substrate and a semiconductor device and an insertion substrate which are arranged on the substrate. The interposer substrate 3 includes a wiring pattern therein. A gap is formed between the semiconductor device and the insertion substrate; in an area corresponding to the gap, a reinforcing member (a metallic film 7) is formed to increase strength of the wiring pattern.Type: GrantFiled: February 28, 2007Date of Patent: October 12, 2010Assignee: NEC CorporationInventors: Takao Yamazaki, Yoshimichi Sogawa, Toshiaki Shironouchi, Kenji Ohyachi
-
Publication number: 20100246144Abstract: The present invention is directed to provide a semiconductor package and the like realizing reduced manufacturing cost and improved reliability by enhancing a ground line and/or a power supply line. A semiconductor package 50 includes: a semiconductor device 1 including a circuit face on which an external electrode is formed; an insertion substrate 2 forming a housing part in which the semiconductor device 1 is disposed; and an interposer substrate 5 including a wiring pattern 7 and whose both ends are bent along the insertion substrate 2. The insertion substrate 2 is made of a conductive material and is electrically connected to a ground line or a power supply line in the wiring pattern 7 in the interposer substrate 5.Type: ApplicationFiled: January 25, 2007Publication date: September 30, 2010Applicant: NEC CORPORATIONInventors: Takao Yamazaki, Yoshimichi Sogawa, Tomohiro Nishiyama
-
Patent number: 7795585Abstract: A vacuum package has a chamber in which pressure is reduced to less than the atmospheric pressure, a functional component sealed in the chamber, and a material forming at least a part of the chamber. The material has at least one through hole to evacuate the chamber. In a cross section perpendicular to the material taken along the through hole, an edge portion of the material forming the through hole has an obtuse angle. The through hole is sealed with a sealing material.Type: GrantFiled: November 26, 2008Date of Patent: September 14, 2010Assignee: NEC CorporationInventors: Yoshimichi Sogawa, Takao Yamazaki, Masahiko Sano, Seiji Kurashina, Yuji Akimoto
-
Patent number: 7594644Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: GrantFiled: November 7, 2005Date of Patent: September 29, 2009Assignee: NEC CorporationInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
-
Publication number: 20090174052Abstract: In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni.Type: ApplicationFiled: May 22, 2007Publication date: July 9, 2009Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Yoshimichi Sogawa, Takao Yamazaki, Nobuaki Takahashi
-
Publication number: 20090140146Abstract: A vacuum package has a chamber in which pressure is reduced to less than the atmospheric pressure, a functional component sealed in the chamber, and a material forming at least a part of the chamber. The material has at least one through hole to evacuate the chamber. In a cross section perpendicular to the material taken along the through hole, an edge portion of the material forming the through hole has an obtuse angle. The through hole is sealed with a sealing material.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: NEC CorporationInventors: Yoshimichi SOGAWA, Takao YAMAZAKI, Masahiko SANO, Seiji KURASHINA, Yuji AKIMOTO
-
Publication number: 20090065921Abstract: There is provided an electronic device package and the like in which it is not likely that damage occurs in a wiring pattern of an interposer substrate in a gap section formed, for example, between an electronic device and an insertion substrate. The semiconductor package in accordance with the present invention is a package of fan-out type including an interposer substrate 3 and a semiconductor device 1 and an insertion substrate 18 which are arranged on the substrate 3. The interposer substrate 3 includes a wiring pattern 6 therein. A gap 8 is formed between the semiconductor device 1 and the insertion substrate 18; in an area corresponding to the gap, a reinforcing member (a metallic film 7) is formed to increase strength of the wiring pattern 6.Type: ApplicationFiled: February 28, 2007Publication date: March 12, 2009Inventors: Takao Yamazaki, Yoshimichi Sogawa, Toshiaki Shironouchi, Kenji Ohyachi
-
Publication number: 20080224271Abstract: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a, 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c, 3d to extend through terminal pad 2a, semiconductor substrate 1, and terminal pad 2b. Insulating layer 4 made of SiO2, SiN, SiO, or the like is formed on the inner surfaces of throughholes 9. Buffer layer 5 made of a conductive adhesive is formed to cover insulating layer 4 and terminal pads 2a, 2b in openings 3c, 3d. Further, conductive layer 6 made of a metal film is formed on buffer layer 5 by electrolytic plating, non-electrolytic plating, or the like.Type: ApplicationFiled: December 21, 2005Publication date: September 18, 2008Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Yoshimichi Sogawa, Takao Yamazaki, Ichirou Hazeyama, Sakae Kitajou, Nobuaki Takahashi
-
Publication number: 20080001288Abstract: A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 ?m, and the low-elasticity particles have a diameter of, e.g., 1 ?m. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.Type: ApplicationFiled: November 25, 2005Publication date: January 3, 2008Inventors: Yoshimichi Sogawa, Takao Yamazaki, Nobuaki Takahashi
-
Patent number: 7230328Abstract: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.Type: GrantFiled: November 19, 2003Date of Patent: June 12, 2007Assignee: NEC CorporationInventors: Ichiro Hazeyama, Yoshimichi Sogawa, Takao Yamazaki, Sakae Kitajo
-
Publication number: 20060055053Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: ApplicationFiled: November 7, 2005Publication date: March 16, 2006Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
-
Publication number: 20060049495Abstract: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.Type: ApplicationFiled: November 19, 2003Publication date: March 9, 2006Applicant: NEC CORPORATIONInventors: Ichiro Hazeyama, Yoshimichi Sogawa, Takao Yamazaki, Sakae Kitajo
-
Patent number: 6998704Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: GrantFiled: August 21, 2003Date of Patent: February 14, 2006Assignee: NEC CorporationInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
-
Publication number: 20040115920Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: ApplicationFiled: August 21, 2003Publication date: June 17, 2004Applicant: NEC CORPORATIONInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda