Patents by Inventor Yoshinao Kawasaki

Yoshinao Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6253117
    Abstract: A vacuum processing apparatus is composed of a cassette block and a vacuum processing block. The cassette block has a cassette table for mounting a plurality of cassettes containing a sample and an atmospheric transfer means. The vacuum processing block has a plurality of processing chambers for performing vacuum processing to the sample and a vacuum transfer means for transferring the sample. Both of the plan views of the cassette block and the vacuum processing block are nearly rectangular, and the width of the cassette block is designed larger than the width of the vacuum processing block, and the plan view of the vacuum processing apparatus is formed in an L-shape or a T-shape.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: June 26, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Soraoka, Ken Yoshioka, Yoshinao Kawasaki
  • Patent number: 6188935
    Abstract: A vacuum processing apparatus is composed of a cassette block and a vacuum processing block. The cassette block has a cassette table for mounting a plurality of cassettes containing a sample and an atmospheric transfer means. The vacuum processing block has a plurality of processing chambers for performing vacuum processing on the sample and a vacuum transfer means for transferring the sample. Both of the plan views of the cassette block and the vacuum processing block are nearly rectangular, and the width of the cassette block is designed to be larger than the width of the vacuum processing block, and the overall plan view of the vacuum processing apparatus is formed in an L-shape or a T-shape.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: February 13, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Soraoka, Ken Yoshioka, Yoshinao Kawasaki
  • Patent number: 6169324
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: January 2, 2001
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6165377
    Abstract: A plasma etching method includes the steps of placing a sample having metal a wiring portion on a sample table in a vacuum vessel, evacuating the vacuum vessel to establish a reduced pressure in the vacuum vessel, introducing an etching gas into the vacuum vessel while continuing to evacuate the vacuum vessel to maintain the reduced pressure in the vacuum vessel, and generating a plasma from the etching gas under the reduced pressure in the vacuum vessel using radio-frequency power. The plasma etches the metal wiring portion, and a residue forms on the metal wiring portion during the etching of the metal wiring portion by the plasma. The method further includes the step of applying to the sample table a bias voltage which periodically changes between two different voltages during the etching of the metal wiring portion by the plasma to remove the residue from the metal wiring portion.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: December 26, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hironobu Kawahara, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama
  • Patent number: 6127255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: October 3, 2000
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6077788
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus, the samples being selectively etched through use of a resist mask), (b) for removing (ashing) the resist mask, (c) for wet-processing of the samples and (d) for dry-processing the samples. Samples are passed sequentially from a supply cassette (containing a plurality of samples) to the plasma etching apparatus, through the other apparatus and to a discharge cassette (which can hold a plurality of the samples). At least two of the samples can be processed simultaneously in a path from (and including), the plasma etching apparatus to (and including) the wet-processing structure.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 20, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinao Kawasaki, Hironobu Kawahara, Yoshiaki Sato, Ryooji Fukuyama, Kazuo Nojiri, Yoshimi Torii
  • Patent number: 6046425
    Abstract: A plasma processing apparatus includes a plasma processing chamber defining a plasma region. The plasma processing chamber has an inner metallic portion defining at least a portion of the plasma region. The plasma processing apparatus also includes a sample table disposed in the plasma region for holding a sample to be subjected to plasma processing, elements for applying an AC voltage to the sample table, elements for generating a plasma, including a region of intense plasma, in the plasma region independently of the AC voltage applied to the sample table such that the AC voltage applied to the sample table has no effect on the generation of the plasma, and an insulator having a thickness of several tens to several hundreds of micrometers (.mu.m) disposed on the inner metallic portion of the plasma processing chamber in a neighborhood of the region of intense plasma.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 4, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Tetsunori Kaji, Takashi Fujii, Motohiko Yoshigai, Yoshinao Kawasaki, Masaharu Nishiumi
  • Patent number: 6036816
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 14, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Kojima, Yoshimi Torii, Michimasa Hunabashi, Kazuyuki Suko, Takashi Yamada, Keizo Kuroiwa, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5952245
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yoshimi Torii, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5914051
    Abstract: A microwave plasma processing method and apparatus of the type wherein a waveguide section includes electric discharge means isolated from a waveguide for the propagation of microwaves and having a plasma generation region therein, which method and apparatus are well suited for subjecting samples, such as semiconductor device substrates, to an etching process, a film forming process, etc. The microwaves are introduced into the electric discharge means in correspondence with only the traveling direction thereof, whereby uniformity in a plasma density distribution corresponding to the surface to-be-processed of the sample can be sharply enhanced, so that the sample processed by utilizing such plasma can attain an enhanced processing homogeneity within the surface to-be-processed.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: June 22, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Kanai, Yoshinao Kawasaki, Kazuaki Ichihashi, Seiichi Watanabe, Makoto Nawata
  • Patent number: 5900162
    Abstract: The present invention relates to a plasma etching method and apparatus, and more particularly to a plasma etching method and apparatus which are well suited for etching the samples of semiconductor device substrates, etc. In cooling a sample to a temperature not higher than 0.degree. C. which is a minimum temperature of water and subjecting the sample to an etching process with a gas plasma, an acceleration voltage which accelerates ions in the gas plasma toward the sample is repeatedly changed, whereby in a process based on low-temperature etching, an etching process producing no residue, being anisotropic and being highly selective is realized.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: May 4, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hironobu Kawahara, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama
  • Patent number: 5868854
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: December 8, 1992
    Date of Patent: February 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Kojima, Yoshimi Torii, Michimasa Hunabashi, Kazuyuki Suko, Takashi Yamada, Keizo Kuroiwa, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5855726
    Abstract: A vacuum processing apparatus is composed of a cassette block and a vacuum processing block. The cassette block has a cassette table for mounting a plurality of cassettes containing a sample and an atmospheric transfer means. The vacuum processing block has a plurality of processing chambers for performing vacuum processing on the sample and a vacuum transfer means for transferring the sample. Both of the plan views of the cassette block and the vacuum processing block are nearly rectangular, and the width of the cassette block is designed to be larger than the width of the vacuum processing block, and the overall plan view of the vacuum processing apparatus is formed in an L-shape or a T-shape.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: January 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Soraoka, Ken Yoshioka, Yoshinao Kawasaki
  • Patent number: 5811316
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 22, 1998
    Assignees: Hitachi. Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5804033
    Abstract: The present invention relates to a microwave plasma processing method and apparatus. According to the present invention, the microwaves are introduced into the electric discharge means in correspondence with only the traveling direction thereof, whereby uniformity in a plasma density distribution corresponding to the surface to-be-processed of the sample can be sharply enhanced, so that the sample processed by utilizing such plasma can attain an enhanced processing homogeneity within the surface to be processed. In addition, homogeneity and stability of the plasma are improved by inserting a cavity resonator between the microwave generator and plasma processing (plasma generating) chamber, and coupling the cavity resonator and plasma processing chamber such that microwaves substantially only of a desired mode (e.g., TE.sub.11) pass into the plasma processing chamber. Such coupling to provide microwaves substantially only of circular TE.sub.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Kanai, Yoshinao Kawasaki, Kazuaki Ichihashi, Seiichi Watanabe, Makoto Nawata, Muneo Furuse, Tetsunori Kaji
  • Patent number: 5785807
    Abstract: The present invention relates to a microwave plasma processing method and apparatus. More particularly, it relates to a microwave plasma processing method and apparatus of the type wherein a waveguide section includes electric discharge means isolated from a waveguide for the propagation of microwaves and having a plasma generation region therein, which method and apparatus are well suited for subjecting samples, such as semiconductor device substrates, to an etching process, a film forming process, etc. According to the present invention, the microwaves are introduced into the electric discharge means in correspondence with only the traveling direction thereof, whereby uniformity in a plasma density distribution corresponding to the surface to-be-processed of the sample can be sharply enhanced, so that the sample processed by utilizing such plasma can attain an enhanced processing homogeneity within the surface to-be-processed.
    Type: Grant
    Filed: September 26, 1991
    Date of Patent: July 28, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Saburo Kanai, Yoshinao Kawasaki, Kazuaki Ichihashi, Seiichi Watanabe, Makoto Nawata
  • Patent number: 5780882
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: July 14, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5739589
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: April 14, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5646489
    Abstract: A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: July 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Kakehi, Yoshinao Kawasaki, Keizo Suzuki, Kazuo Nojiri, Hiromichi Enami, Tetsunori Kaji, Seiichi Watanabe, Yoshifumi Ogawa
  • Patent number: 5557147
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: September 17, 1996
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corporation
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane