Patents by Inventor Yoshinari Ikeda

Yoshinari Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142559
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: November 12, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Publication number: 20240304537
    Abstract: An electronic device, including: a conductive element having a conductive region on a front surface thereof; a fixing element having a fixing region on a front surface thereof, the fixing element being located apart from the conductive element in a plan view of the electronic device; and a wiring member having a flat plate shape. The wiring member includes a first portion bonded to the conductive region of the conductive element, a second portion fixed to the fixing region of the fixing element, and an inclined portion between the first portion and the second portion, the inclined portion being elastically deformable. In a side view of the electronic device, the conductive region of the conductive element and the fixing region of the fixing element are at different heights in a thickness direction of the electronic device.
    Type: Application
    Filed: February 22, 2024
    Publication date: September 12, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
  • Patent number: 12080612
    Abstract: A semiconductor device includes: an insulated circuit substrate; a power semiconductor element mounted on the insulated circuit substrate; a first terminal having a plate-like shape having a first main surface and electrically connected to the power semiconductor element; a second terminal having a second main surface opposed to the first main surface of the first terminal and electrically connected to the power semiconductor element; an insulating sheet interposed between the first main surface and the second main surface; and a conductive film provided on at least one of the first main surface side and the second main surface side of the insulating sheet.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: September 3, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi Taniguchi, Yoshinari Ikeda, Ryoichi Kato, Yuma Murata, Akito Nakagome
  • Patent number: 12072155
    Abstract: A cooling device includes a body having a flow passage for a heating medium that passes through the body, a first header made of a resin that has an inlet and covers a first end, and a second header made of a resin that has an outlet and covers a second end. The body has a front face, a back face, a first side face, and a second side face. The body and the first header are bonded to a first bonding face, a second bonding face, a third bonding face, and a fourth bonding face. The third bonding face is a curved surface that protrudes toward a +Y side. The fourth bonding face is a curved surface that protrudes toward a ?Y side.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 27, 2024
    Assignees: NIPPON LIGHT METAL COMPANY, LTD., FUJI ELECTRIC CO., LTD., KOJIN CO., LTD.
    Inventors: Akihito Aoki, Eiji Anzai, Yoshinari Ikeda, Hiromichi Gohara, Ryoichi Kato, Michihiro Inaba, Tetsuya Sunago
  • Publication number: 20240178113
    Abstract: A positive electrode circuit pattern layer and a negative electrode circuit pattern layer each have a terminal region extending in a long-side direction of a rectangular insulating plate. Thicknesses of a positive electrode bonding region of a positive electrode terminal and a negative electrode bonding region of a negative electrode terminal are respectively less than thicknesses of the terminal regions of the positive electrode circuit pattern layer and the negative electrode circuit pattern layer. The lengths in the long-side direction of the positive electrode bonding region of the positive electrode terminal and the negative electrode bonding region of the negative electrode terminal are respectively greater than or equal to half the lengths in the long-side direction of the terminal regions of the positive electrode circuit pattern layer and negative electrode circuit pattern layer.
    Type: Application
    Filed: September 26, 2023
    Publication date: May 30, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA
  • Publication number: 20240128241
    Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
  • Patent number: 11887925
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Publication number: 20240006303
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Yuma MURATA
  • Publication number: 20240006287
    Abstract: A semiconductor device includes an insulated circuit substrate, a semiconductor chip, a printed circuit board, an interposer, and a sealing member, the interposer including a plurality of post electrodes each having one end bonded to the semiconductor chip via a solder layer, an insulating layer provided to be separately opposed to the semiconductor chip and provided with a first penetration hole filled with part of the solder layer, and a conductor layer provided to be opposed to the printed circuit board and connected to another end of each of the post electrodes via the insulating layer.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
  • Publication number: 20230411313
    Abstract: A semiconductor device includes: an insulated circuit substrate; a semiconductor chip provided on the insulated circuit substrate; a first external connection terminal provided on the insulated circuit substrate; a relay terminal provided on the insulated circuit substrate; a printed circuit board arranged over the semiconductor chip and connected to the first external connection terminal and the relay terminal; and a first snubber circuit provided on the printed circuit board and having one end connected to the first external connection terminal via the printed circuit board and another end connected to the relay terminal via the printed circuit board.
    Type: Application
    Filed: April 24, 2023
    Publication date: December 21, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
  • Publication number: 20230369142
    Abstract: A semiconductor device includes a first input conductive plate on which a plurality of first semiconductor chips arranged in a first direction, a first output conductive plate extending in the first direction and being provided adjacent to the first input conductive plate, a case having first to fourth side walls for accommodating the first input conductive plate and the first output conductive plate, first main current wiring members, each of which connects one of the first output electrodes to a front surface of the first output conductive plate, a first detection terminal disposed in the first side wall, and a first detection wiring member connecting the front surface of the first output conductive plate to the first detection terminal. The first output conductive plate is disposed closer to the first side wall than is the first input conductive plate.
    Type: Application
    Filed: March 9, 2023
    Publication date: November 16, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA, Takaaki TANAKA, Qichen WANG
  • Publication number: 20230307400
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a sintered metal such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Eiji MOCHIZUKI
  • Publication number: 20230260859
    Abstract: A semiconductor device includes a semiconductor module that includes: an insulating circuit board, a semiconductor chip provided on a main surface of the insulating circuit board, and an external connection terminals provided on the main surface of the insulating circuit board; an external printed circuit board provided so as to face a main surface of the semiconductor module, the external printed circuit board having a through hole into which the external connection terminal is inserted; and an elastic member provided between the main surface of the semiconductor module and the external printed circuit board so as to apply a pressing force to the main surface of the semiconductor module.
    Type: Application
    Filed: January 3, 2023
    Publication date: August 17, 2023
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
  • Patent number: 11705419
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: July 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Eiji Mochizuki
  • Publication number: 20230187311
    Abstract: A semiconductor module includes a conductor layer, an insulating plate, a circuit pattern layer, and semiconductor chips disposed in this order. The conductor layer has a first through hole. The insulating plate has a second through hole having an opening size larger than the first through hole at a location facing the first through hole. The circuit pattern layer has an opening having an opening size larger than the second through hole at a location facing the second through hole. When the semiconductor module is connected to a cooling member, heat transfer medium is disposed between the conductor layer and the cooling member. A screw member is inserted into the opening and second and first through holes and screwed into a screw attachment hole. The screw member presses an area around the first through hole inside the second through hole toward the cooling member.
    Type: Application
    Filed: October 25, 2022
    Publication date: June 15, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA
  • Patent number: 11664342
    Abstract: A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 30, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Tada, Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Patent number: 11658231
    Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 23, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao, Tsunehiro Nakajima
  • Publication number: 20230119240
    Abstract: A semiconductor device includes: an insulated circuit substrate; a power semiconductor element mounted on the insulated circuit substrate; a first terminal having a plate-like shape having a first main surface and electrically connected to the power semiconductor element; a second terminal having a second main surface opposed to the first main surface of the first terminal and electrically connected to the power semiconductor element; an insulating sheet interposed between the first main surface and the second main surface; and a conductive film provided on at least one of the first main surface side and the second main surface side of the insulating sheet.
    Type: Application
    Filed: August 24, 2022
    Publication date: April 20, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi TANIGUCHI, Yoshinari IKEDA, Ryoichi KATO, Yuma MURATA, Akito NAKAGOME
  • Patent number: 11545409
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Motohito Hori, Eiji Mochizuki
  • Publication number: 20220406689
    Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; a printed circuit board provided over and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending upward from the conductive plate; a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state; and a sealing member provided to seal the semiconductor chip, the printed circuit board, and the first conductive block.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 22, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO