Patents by Inventor Yoshinobu Asami
Yoshinobu Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950410Abstract: A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.Type: GrantFiled: June 13, 2022Date of Patent: April 2, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshinobu Asami
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Publication number: 20240008293Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.Type: ApplicationFiled: May 31, 2023Publication date: January 4, 2024Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takanori MATSUZAKI, Yoshinobu ASAMI, Daisuke MATSUBAYASHI, Tatsuya ONUKI
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Patent number: 11742431Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.Type: GrantFiled: October 14, 2021Date of Patent: August 29, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yoshinobu Asami, Takahisa Ishiyama, Motomu Kurata, Ryo Tokumaru, Noritaka Ishihara, Yusuke Nonaka
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Patent number: 11696455Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.Type: GrantFiled: October 25, 2021Date of Patent: July 4, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takanori Matsuzaki, Yoshinobu Asami, Daisuke Matsubayashi, Tatsuya Onuki
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Publication number: 20230040161Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.Type: ApplicationFiled: October 7, 2022Publication date: February 9, 2023Inventor: Yoshinobu ASAMI
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Patent number: 11469330Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.Type: GrantFiled: June 1, 2020Date of Patent: October 11, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshinobu Asami
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Publication number: 20220310628Abstract: A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventor: Yoshinobu ASAMI
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Patent number: 11374012Abstract: A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.Type: GrantFiled: June 29, 2018Date of Patent: June 28, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshinobu Asami
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Publication number: 20220199831Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: ApplicationFiled: February 3, 2022Publication date: June 23, 2022Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
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Publication number: 20220157818Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.Type: ApplicationFiled: October 25, 2021Publication date: May 19, 2022Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takanori MATSUZAKI, Yoshinobu ASAMI, Daisuke MATSUBAYASHI, Tatsuya ONUKI
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Patent number: 11276782Abstract: A semiconductor device capable of miniaturization or high integration and manufacture of a semiconductor device are provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator and first and second conductors over the oxide; a third conductor over the second insulator; a fourth conductor over the first conductor; a fifth conductor over the second conductor; a third insulator over the first insulator and the first and second conductors; a fourth insulator over the second and third insulators and the third conductor; and a fifth insulator over the fourth insulator. The first and second conductors are provided to face each other with the second insulator therebetween. The second insulator is provided along an inner wall of an opening provided in the third insulator, facing side surfaces of the first and second conductors, and a top surface of the oxide.Type: GrantFiled: March 15, 2018Date of Patent: March 15, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshinobu Asami
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Publication number: 20220059701Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.Type: ApplicationFiled: October 14, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yoshinobu ASAMI, Takahisa ISHIYAMA, Motomu KURATA, Ryo TOKUMARU, Noritaka ISHIHARA, Yusuke NONAKA
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Patent number: 11245039Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: GrantFiled: April 9, 2019Date of Patent: February 8, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
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Patent number: 11164871Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.Type: GrantFiled: August 29, 2018Date of Patent: November 2, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takanori Matsuzaki, Yoshinobu Asami, Daisuke Matsubayashi, Tatsuya Onuki
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Patent number: 11152513Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.Type: GrantFiled: August 24, 2018Date of Patent: October 19, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yoshinobu Asami, Takahisa Ishiyama, Motomu Kurata, Ryo Tokumaru, Noritaka Ishihara, Yusuke Nonaka
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Patent number: 11024743Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: GrantFiled: April 9, 2019Date of Patent: June 1, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
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Publication number: 20210159342Abstract: A semiconductor device capable of miniaturization or high integration and manufacture of a semiconductor device are provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator and first and second conductors over the oxide; a third conductor over the second insulator; a fourth conductor over the first conductor; a fifth conductor over the second conductor; a third insulator over the first insulator and the first and second conductors; a fourth insulator over the second and third insulators and the third conductor; and a fifth insulator over the fourth insulator. The first and second conductors are provided to face each other with the second insulator therebetween. The second insulator is provided along an inner wall of an opening provided in the third insulator, facing side surfaces of the first and second conductors, and a top surface of the oxide.Type: ApplicationFiled: March 15, 2018Publication date: May 27, 2021Inventor: Yoshinobu ASAMI
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Publication number: 20210126130Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.Type: ApplicationFiled: August 24, 2018Publication date: April 29, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yoshinobu ASAMI, Takahisa ISHIYAMA, Motomu KURATA, Ryo TOKUMARU, Noritaka ISHIHARA, Yusuke NONAKA
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Publication number: 20200295196Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventor: Yoshinobu ASAMI
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Publication number: 20200227562Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide; a first conductor and a second conductor apart from each other over the oxide; a first insulator over the first conductor and the second conductor, in which an opening is formed to overlap with a region between the first conductor and the second conductor; a third conductor in the opening; and a second insulator between the oxide, the first conductor, the second conductor, and the first insulator and the third conductor. The second insulator has a first thickness between the oxide and the third conductor, and has a second thickness between the first conductor or the second conductor and the third conductor. The first thickness is smaller than the second thickness.Type: ApplicationFiled: July 26, 2018Publication date: July 16, 2020Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Yoshinobu ASAMI