Patents by Inventor Yoshinobu Kunitomo
Yoshinobu Kunitomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230125127Abstract: A metal titanium production apparatus includes: a reductor that subjects titanium tetrachloride to a reduction process in presence of bismuth and magnesium to obtain a liquid alloy containing titanium and the bismuth; a segregator that subjects the liquid alloy to a segregation process to obtain a precipitate; and a distillator that subjects the precipitate to a distillation process to obtain metal titanium, and the distillator sets an atmosphere so as to preferentially vaporize the bismuth attached to the precipitate and then sets the atmosphere so as to vaporize the bismuth forming the precipitate.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Applicants: KYOTO UNIVERSITY, IHI CORPORATIONInventors: Tetsuya UDA, Yoshinobu KUNITOMO, Akihiro KISHIMOTO, Kazuhiro KUMAMOTO, Akihiro SATO, Yasushi DODO, Takuya HASHIMOTO, Akihiko YOSHIMURA
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Publication number: 20210230715Abstract: A metal titanium production apparatus includes: a reductor that subjects titanium tetrachloride to a reduction process in presence of bismuth and magnesium to obtain a liquid alloy containing titanium and the bismuth; a segregator that subjects the liquid alloy to a segregation process to obtain a precipitate; and a distillator that subjects the precipitate to a distillation process to obtain metal titanium, and the distillator sets an atmosphere so as to preferentially vaporize the bismuth attached to the precipitate and then sets the atmosphere so as to vaporize the bismuth forming the precipitate.Type: ApplicationFiled: April 25, 2019Publication date: July 29, 2021Applicants: KYOTO UNIVERSITY, IHI CORPORATIONInventors: Tetsuya UDA, Yoshinobu KUNITOMO, Akihiro KISHIMOTO, Kazuhiro KUMAMOTO, Akihiro SATO, Yasushi DODO, Takuya HASHIMOTO, Akihiko YOSHIMURA
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Patent number: 7286729Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.Type: GrantFiled: April 4, 2006Date of Patent: October 23, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo
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Publication number: 20060222285Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.Type: ApplicationFiled: April 4, 2006Publication date: October 5, 2006Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo
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Patent number: 7078818Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: GrantFiled: January 30, 2004Date of Patent: July 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Publication number: 20040183173Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: ApplicationFiled: January 30, 2004Publication date: September 23, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaka Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Patent number: 6777796Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: GrantFiled: December 17, 2002Date of Patent: August 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Patent number: 6707143Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: GrantFiled: December 17, 2002Date of Patent: March 16, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Patent number: 6693347Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: GrantFiled: December 17, 2002Date of Patent: February 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Publication number: 20030089972Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: ApplicationFiled: December 17, 2002Publication date: May 15, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Publication number: 20030085458Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: ApplicationFiled: December 17, 2002Publication date: May 8, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Publication number: 20030085457Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: ApplicationFiled: December 17, 2002Publication date: May 8, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Patent number: 6509638Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: GrantFiled: September 6, 2001Date of Patent: January 21, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Publication number: 20020027275Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.Type: ApplicationFiled: September 6, 2001Publication date: March 7, 2002Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
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Patent number: 5622590Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.Type: GrantFiled: April 28, 1995Date of Patent: April 22, 1997Assignee: Matsushita Electronics CorporationInventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
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Patent number: 5550408Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in a matrix. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.Type: GrantFiled: March 23, 1995Date of Patent: August 27, 1996Assignee: Matsushita Electronics CorporationInventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
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Patent number: 5436503Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.Type: GrantFiled: November 17, 1993Date of Patent: July 25, 1995Assignee: Matsushita Electronics CorporationInventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
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Patent number: 4958216Abstract: Disclosed is a package for housing semiconductor elements, which comprises an insulating substrate having in the interior thereof a cavity for attaching and housing semiconductor elements and a lid member covering said cavity, wherein the insulating substrate is composed of a mullite sintered body comprising 70 to 95% by weight of mullite and 5 to 30% by weight, as the total content, of silica (SiO.sub.2) and at least one member selected from the group consisting of magnesia (MgO) and calcia (CaO), and SiO.sub.2, MgO and CaO are present in the following composition expressed by % by weight based on the three components:100>SiO.sub.2 .gtoreq.60,40.gtoreq.MgO.gtoreq.O and40.gtoreq.CaO.gtoreq.O.Type: GrantFiled: May 24, 1988Date of Patent: September 18, 1990Assignee: Kyocera CorporationInventors: Jun Tanaka, Hitoshi Oikawa, Yoshinobu Kunitomo, Masami Terasawa
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Patent number: D501664Type: GrantFiled: December 3, 2003Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Yoshinobu Kunitomo, Mutsuo Tshuji, Koichi Yamauchi
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Patent number: D505964Type: GrantFiled: December 3, 2003Date of Patent: June 7, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Yoshinobu Kunitomo, Mutsuo Tsuji, Koichi Yamauchi