Patents by Inventor Yoshinobu Kunitomo

Yoshinobu Kunitomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230125127
    Abstract: A metal titanium production apparatus includes: a reductor that subjects titanium tetrachloride to a reduction process in presence of bismuth and magnesium to obtain a liquid alloy containing titanium and the bismuth; a segregator that subjects the liquid alloy to a segregation process to obtain a precipitate; and a distillator that subjects the precipitate to a distillation process to obtain metal titanium, and the distillator sets an atmosphere so as to preferentially vaporize the bismuth attached to the precipitate and then sets the atmosphere so as to vaporize the bismuth forming the precipitate.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Applicants: KYOTO UNIVERSITY, IHI CORPORATION
    Inventors: Tetsuya UDA, Yoshinobu KUNITOMO, Akihiro KISHIMOTO, Kazuhiro KUMAMOTO, Akihiro SATO, Yasushi DODO, Takuya HASHIMOTO, Akihiko YOSHIMURA
  • Publication number: 20210230715
    Abstract: A metal titanium production apparatus includes: a reductor that subjects titanium tetrachloride to a reduction process in presence of bismuth and magnesium to obtain a liquid alloy containing titanium and the bismuth; a segregator that subjects the liquid alloy to a segregation process to obtain a precipitate; and a distillator that subjects the precipitate to a distillation process to obtain metal titanium, and the distillator sets an atmosphere so as to preferentially vaporize the bismuth attached to the precipitate and then sets the atmosphere so as to vaporize the bismuth forming the precipitate.
    Type: Application
    Filed: April 25, 2019
    Publication date: July 29, 2021
    Applicants: KYOTO UNIVERSITY, IHI CORPORATION
    Inventors: Tetsuya UDA, Yoshinobu KUNITOMO, Akihiro KISHIMOTO, Kazuhiro KUMAMOTO, Akihiro SATO, Yasushi DODO, Takuya HASHIMOTO, Akihiko YOSHIMURA
  • Patent number: 7286729
    Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo
  • Publication number: 20060222285
    Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.
    Type: Application
    Filed: April 4, 2006
    Publication date: October 5, 2006
    Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo
  • Patent number: 7078818
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: July 18, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20040183173
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 23, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaka Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 6777796
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 6707143
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 6693347
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20030089972
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 15, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20030085458
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 8, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20030085457
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 8, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 6509638
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: January 21, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20020027275
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 7, 2002
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 5622590
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5550408
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in a matrix. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: August 27, 1996
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5436503
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: July 25, 1995
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 4958216
    Abstract: Disclosed is a package for housing semiconductor elements, which comprises an insulating substrate having in the interior thereof a cavity for attaching and housing semiconductor elements and a lid member covering said cavity, wherein the insulating substrate is composed of a mullite sintered body comprising 70 to 95% by weight of mullite and 5 to 30% by weight, as the total content, of silica (SiO.sub.2) and at least one member selected from the group consisting of magnesia (MgO) and calcia (CaO), and SiO.sub.2, MgO and CaO are present in the following composition expressed by % by weight based on the three components:100>SiO.sub.2 .gtoreq.60,40.gtoreq.MgO.gtoreq.O and40.gtoreq.CaO.gtoreq.O.
    Type: Grant
    Filed: May 24, 1988
    Date of Patent: September 18, 1990
    Assignee: Kyocera Corporation
    Inventors: Jun Tanaka, Hitoshi Oikawa, Yoshinobu Kunitomo, Masami Terasawa
  • Patent number: D501664
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Yoshinobu Kunitomo, Mutsuo Tshuji, Koichi Yamauchi
  • Patent number: D505964
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Yoshinobu Kunitomo, Mutsuo Tsuji, Koichi Yamauchi