Patents by Inventor Yoshinobu Miyamoto

Yoshinobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069877
    Abstract: An organic EL display device is provided with an eaves body that includes a protruding portion outside a display region on a TFT substrate, along an edge portion on which a first inorganic layer and a second inorganic layer of a sealing film are provided. The first inorganic layer and the second inorganic layer cover the protruding portion and are split apart below the protruding portion facing a wall surface of the eaves body.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 20, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Sonoda, Takeshi Hirase, Hisao Ochi, Takashi Ochi, Tohru Senoo, Akihiro Matsui, Jumpei Takahashi, Yoshinobu Miyamoto
  • Publication number: 20210210724
    Abstract: An organic EL display device includes an organic EL element disposed on a flattening film, and a sealing film disposed over the organic EL element, a display region, and a frame region disposed around the display region. The frame region includes a plurality of mask spacers. The flattening film has a recess disposed between the display region and the mask spacers adjacent to the display region. The recess is filled with an organic film.
    Type: Application
    Filed: May 23, 2018
    Publication date: July 8, 2021
    Inventors: TOHRU SENOO, TAKESHI HIRASE, HISAO OCHI, TAKASHI OCHI, TOHRU SONODA, AKIHIRO MATSUI, YOSHINOBU MIYAMOTO, JUMPEI TAKAHASHI
  • Publication number: 20210135159
    Abstract: A display wiring line provided on a resin substrate layer, a flattening film covering the display wiring line, and an organic EL element provided on the flattening film are provided. The display wiring line includes first to third conductive layers layered sequentially from the resin substrate layer side. In the display wiring line, the second conductive layer is formed with a width smaller than a width of each of the first conductive layer and the third conductive layer, and a portion of a perimeter edge surface corresponding to the second conductive layer includes a recessed portion, and a resin cover covering a perimeter edge surface of the second conductive layer is provided in the recessed portion in a portion of the display wiring line exposed from the flattening film.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 6, 2021
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tohru SENOO, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SONODA, Akihiro MATSUI, Jumpei TAKAHASHI, Yoshinobu MIYAMOTO, Takeshi YANEDA
  • Publication number: 20210108310
    Abstract: In a A film forming mask includes a plurality of first openings are formed on the film-forming a thin film pattern on a substrate. A second opening is formed around each of the plurality of first openings An opening area of the second opening is smaller than an opening area of each of the plurality of first openings.
    Type: Application
    Filed: March 20, 2018
    Publication date: April 15, 2021
    Inventors: YOSHINOBU MIYAMOTO, TOHRU SONODA
  • Publication number: 20210028410
    Abstract: A method for manufacturing a display device, includes: forming a thin film transistor layer; forming a light-emitting element layer; and forming a sealing layer, wherein the display device includes: a display region; and a frame region being a non-display region formed on an outer side of the display region, during forming the thin film transistor layer, a mask spacer is formed on an outer side of a cutting surface corresponding to an end face of the frame region, the mask spacer on which a deposition mask is placed, during forming the sealing layer, at least one inorganic film is formed through use of the deposition mask, and the at least one inorganic film covers the display region, and is formed on an inner side of the cutting surface.
    Type: Application
    Filed: March 28, 2018
    Publication date: January 28, 2021
    Inventors: AKIHIRO MATSUI, TAKESHI HIRASE, YOSHINOBU MIYAMOTO, TOHRU SONODA, HISAO OCHI, TOHRU SENOO, JUMPEI TAKAHASHI, TAKASHI OCHI
  • Publication number: 20210005842
    Abstract: Each of lead wiring lines that constitutes a TFT layer and is provided to extend parallel to each other in a frame region extends to intersect with a perimeter edge surface of a first organic film that constitutes the TFT layer and is provided on each of the lead wiring lines. A second organic film is provided to cover a lower portion of the perimeter edge surface of the first organic film and each of the lead wiring lines on a side of the perimeter edge surface of the first organic film, the lead wiring lines extending from the perimeter edge surface of the first organic film.
    Type: Application
    Filed: March 2, 2018
    Publication date: January 7, 2021
    Inventors: JUMPEI TAKAHASHI, AKIHIRO MATSUI, TAKASHI OCHI, TOHRU SONODA, YOSHINOBU MIYAMOTO
  • Patent number: 10608062
    Abstract: A bank (BK1b) and a bank (BK1a) having a height less than a height of the bank (BK1b) are intermittently provided on a bank (BK1) covering a peripheral portion of each first electrode (21) of a light emitting element.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 31, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jumpei Takahashi, Takeshi Hirase, Hisao Ochi, Takashi Ochi, Tohru Senoo, Tohru Sonoda, Akihiro Matsui, Yoshinobu Miyamoto
  • Publication number: 20200091459
    Abstract: The organic EL display device includes a third organic insulating film pattern portion, which includes a groove on an upper surface thereof, between a display region and at least part of an edge portion of a TFT substrate. A first inorganic layer and a second inorganic layer of a sealing film cover the third organic insulating film pattern portion and at least part of the edge portion in a plan view, and are split apart in the groove.
    Type: Application
    Filed: March 27, 2017
    Publication date: March 19, 2020
    Inventors: Tohru SENOO, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SONODA, Jumpei TAKAHASHI, Akihiro MATSUI, Yoshinobu MIYAMOTO
  • Patent number: 10573853
    Abstract: A method of manufacturing a display device includes a step of forming a first inorganic film constituting a sealing film and a step of forming an organic film constituting the sealing film. Between these steps, the method further includes a foreign matter inspection step of inspecting a substrate surface on which the first inorganic film has been formed and identifying the location of a foreign matter adhering to the substrate surface, and a partial ejection step of using an ink-jet method to eject ink to be formed a part of the organic film at the location of the foreign matter on the substrate surface identified in the foreign matter inspection step.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 25, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Senoo, Takeshi Hirase, Hisao Ochi, Takashi Ochi, Tohru Sonoda, Jumpei Takahashi, Akihiro Matsui, Yoshinobu Miyamoto
  • Publication number: 20200006702
    Abstract: An organic EL display device is provided with an eaves body that includes a protruding portion outside a display region on a TFT substrate, along an edge portion on which a first inorganic layer and a second inorganic layer of a sealing film are provided. The first inorganic layer and the second inorganic layer cover the protruding portion and are split apart below the protruding portion facing a wall surface of the eaves body.
    Type: Application
    Filed: March 3, 2017
    Publication date: January 2, 2020
    Inventors: Tohru SONODA, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SENOO, Akihiro MATSUI, Jumpei TAKAHASHI, Yoshinobu MIYAMOTO
  • Publication number: 20190372061
    Abstract: A method of manufacturing a display device includes a step of forming a first inorganic film constituting a sealing film and a step of forming an organic film constituting the sealing film. Between these steps, the method further includes a foreign matter inspection step of inspecting a substrate surface on which the first inorganic film has been formed and identifying the location of a foreign matter adhering to the substrate surface, and a partial ejection step of using an ink-jet method to eject ink to be formed a part of the organic film at the location of the foreign matter on the substrate surface identified in the foreign matter inspection step.
    Type: Application
    Filed: September 22, 2017
    Publication date: December 5, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tohru SENOO, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SONODA, Jumpei TAKAHASHI, Akihiro MATSUI, Yoshinobu MIYAMOTO
  • Publication number: 20190363146
    Abstract: A bank (BK1b) and a bank (BK1a) having a height less than a height of the bank (BK1b) are intermittently provided on a bank (BK1) covering a peripheral portion of each first electrode (21) of a light emitting element.
    Type: Application
    Filed: March 16, 2017
    Publication date: November 28, 2019
    Inventors: Jumpei TAKAHASHI, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SENOO, Tohru SONODA, Akihiro MATSUI, Yoshinobu MIYAMOTO
  • Publication number: 20190360091
    Abstract: A sheet portion and a first projection are included. The sheet portion has a sheet shape and includes one or more mask openings. The first projection is provided on a surface of the sheet portion the surface is configured to face a substrate, and the first projection has a frame shape and is formed along an edge of at least one of the one or more mask openings. With this configuration, thin films having dimensions conforming to the design dimensions and preventing blurring are formed over the substrate.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 28, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshinobu MIYAMOTO, Takeshi HIRASE, Tohru SONODA, Akihiro MATSUI, Hisao OCHI, Takashi OCHI, Tohru SENOO, Jumpei TAKAHASHI
  • Publication number: 20190363302
    Abstract: A substrate mounting portion includes a low temperature portion whose temperature is adjusted to an atmospheric temperature or lower at a position corresponding to a frame-shaped bank surrounding a pixel formation region of a substrate. An edge width of a sealing layer is narrowed with this configuration.
    Type: Application
    Filed: February 27, 2017
    Publication date: November 28, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Jumpei TAKAHASHI, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SENOO, Tohru SONODA, Akihiro MATSUI, Yoshinobu MIYAMOTO
  • Publication number: 20190319218
    Abstract: In a sealing film in which a first inorganic film, an organic film, and a second inorganic film are layered in that order, a high-wettability region having a relatively high wettability with respect to droplets configured to become the organic film, and a low-wettability region having a relatively low wettability with respect to the droplets, are arranged in an alternating manner on an organic film side surface of the first inorganic film.
    Type: Application
    Filed: September 28, 2017
    Publication date: October 17, 2019
    Inventors: Jumpei TAKAHASHI, Tohru SONODA, Yoshinobu MIYAMOTO
  • Publication number: 20190312228
    Abstract: A first protruding portion that has a surface having liquid-philic properties to an ink material and has a frame shape and a second protruding portion that has a surface having liquid-repellent properties to the ink material, surrounds the first protruding portion such that at least a part of the first protruding portion is located inside, and has a frame shape are formed so as to surround an electro-optical element. Then, the ink material is applied to a region surrounded by the first protruding portion and is cured, and thus an organic layer that seals the electro-optical element is formed.
    Type: Application
    Filed: July 14, 2017
    Publication date: October 10, 2019
    Inventors: Tohru SONODA, Hisao OCHI, Jumpei TAKAHASHI, Tohru SENOO, Takeshi HIRASE, Takashi OCHI, Akihiro MATSUI, Yoshinobu MIYAMOTO
  • Patent number: 9142573
    Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 22, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Yamashita, Tokuo Yoshida, Yoshimasa Chikama, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto
  • Patent number: 9035295
    Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 19, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
  • Patent number: 8975619
    Abstract: The invention relates to co-activated silicate based phosphors. The invention further relates to the method of preparing these phosphors and to the use of these phosphors in electronic and electrooptical devices, in particular in light emitting diodes (LEDs) and solar cells. The invention further relates to illumination units comprising said phosphors.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 10, 2015
    Assignee: Merck Patent GmbH
    Inventors: Hiroshi Okura, Takeo Wakimoto, Koutoku Ohmi, Yoshinobu Miyamoto
  • Patent number: 8698152
    Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno