Abstract: The present invention is directed to provide new PCR measuring method and device. As one embodiment of the present invention, a DNA detection method for detecting DNA in a droplet being present in oil, the droplet containing the DNA and a fluorescent labeled probe, the fluorescent labeled probe being hybridized to the DNA, the method including: a first step of amplifying the DNA in the droplet by a nucleic acid amplification reaction; and a second step of measuring a melting temperature of the fluorescent labeled probe and the DNA in the droplet is provided.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: A hair cosmetic according to the present invention contains, as an active ingredient, a composite of an amino thiol and an organic acid. The amino thiol is at least one compound selected from the group consisting of cysteamine and a salt thereof, and the organic acid is at least one compound selected from the group consisting of fumaric acid, fumarate, maleic acid, and maleate. Such amino thiol and organic acid have been conventionally used as cosmetic materials, and ensure improved safety for users.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.

Abstract: An image processing device includes an image data generation circuit configured to generate n pieces of Bayer-type divisional image data configured by divisional pixel signals having the same divisional arrangement from divisional pixel signals of m×n generated by photoelectric conversion elements at n parts into which each of m pixels is divided, and an image processing circuit configured to perform image processing on the n pieces of Bayer-type divisional image data.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.

Abstract: An image processing device includes an image data generation circuit configured to generate n pieces of Bayer-type divisional image data configured by divisional pixel signals having the same divisional arrangement from divisional pixel signals of m×n generated by photoelectric conversion elements at n parts into which each of m pixels is divided, and an image processing circuit configured to perform image processing on the n pieces of Bayer-type divisional image data.

Abstract: A planetary gear device for a motorcycle transmits a power of a reciprocating combustion engine to a supercharger. The supercharger pressurizes intake air for the combustion engine. The supercharger includes a supercharger rotation shaft and an impeller supported by the supercharger rotation shaft. A planetary gear and an internal gear of the planetary gear device are each composed of a helical gear, and the planetary gear and the internal gear form a helical gear pair. The planetary gear device includes a pressing unit that applies a pressing force in an axial direction to the planetary gear.