Patents by Inventor Yoshinori Deguchi

Yoshinori Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818601
    Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 27, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Publication number: 20200328157
    Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Yoshinori DEGUCHI, Akinobu WATANABE
  • Patent number: 10777507
    Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Publication number: 20200043877
    Abstract: A semiconductor device includes semiconductor substrate having outer peripheral sides in plan view, and at least a pair of first bonding pad and second bonding pad formed over the semiconductor substrate. The second bonding pad has a shape obtained by rotating the first bonding pad by 180 degrees in plan view. The first bonding pad and the second bonding pad are arranged so as to face each other in a first direction crossing the outer peripheral side. The first bonding pad has a first portion and a second portion of rectangular shape in the second direction along the outer peripheral side. A width of the first portion in the first direction is greater than a width of the second portion in the first direction.
    Type: Application
    Filed: July 2, 2019
    Publication date: February 6, 2020
    Inventors: Kentaro SAITO, Takashi MORIYAMA, Yoshinori DEGUCHI
  • Publication number: 20190295930
    Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.
    Type: Application
    Filed: February 21, 2019
    Publication date: September 26, 2019
    Inventors: Yoshinori DEGUCHI, Iwao NATORI, Seiya ISOZAKI
  • Publication number: 20190167135
    Abstract: A biomagnetic measurement apparatus includes a table on which a subject is placed; a biomagnetic detector configured to detect a biomagnetic field of the subject; a supporter configured to support a detection target region from which the biomagnetic field of the subject is detected; a radiation detector provided below the supporter; and a position changer configured to change relative positions of the biomagnetic detector and the detection target region. The supporter has a surface shape that corresponds to a surface of the biomagnetic detector.
    Type: Application
    Filed: November 23, 2018
    Publication date: June 6, 2019
    Applicants: Ricoh Company, Ltd., National University Corporation Tokyo Medical and Dental University
    Inventors: Yoshinori Okada, Yoshihisa Naijo, Hiroshi Deguchi, Taishi Watanabe, Yuki Miyano, Shigenori Kawabata
  • Publication number: 20180374795
    Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.
    Type: Application
    Filed: February 23, 2016
    Publication date: December 27, 2018
    Inventors: Yoshinori DEGUCHI, Akinobu WATANABE
  • Patent number: 10141295
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
  • Publication number: 20180040598
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 8, 2018
    Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
  • Patent number: 9825017
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
  • Publication number: 20170005080
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
  • Patent number: 9490218
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: November 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
  • Publication number: 20160027731
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Patent number: 9230938
    Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
  • Patent number: 9171767
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Grant
    Filed: November 8, 2014
    Date of Patent: October 27, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Publication number: 20150243605
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
  • Patent number: 9053954
    Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: June 9, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
  • Publication number: 20150111317
    Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
    Type: Application
    Filed: December 27, 2014
    Publication date: April 23, 2015
    Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
  • Publication number: 20150076709
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Application
    Filed: November 8, 2014
    Publication date: March 19, 2015
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Patent number: 8945953
    Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi