Patents by Inventor Yoshinori Ieda

Yoshinori Ieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8319267
    Abstract: A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Yoshinori Ieda, Jun Koyama
  • Patent number: 8319269
    Abstract: A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate. The first insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinori Ieda
  • Publication number: 20120273773
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Application
    Filed: April 11, 2012
    Publication date: November 1, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshinori IEDA, Atsuo ISOBE, Yutaka SHIONOIRI, Tomoaki ATSUMI
  • Publication number: 20110316057
    Abstract: It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Motomu KURATA, Shinya SASAGAWA, Fumika TAGUCHI, Yoshinori IEDA
  • Publication number: 20110298027
    Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Atsuo Isobe, Yoshinori Ieda, Kiyoshi Kato, Yuto Yakubo, Yuki Hata
  • Publication number: 20110297928
    Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Atsuo ISOBE, Yoshinori IEDA, Keitaro IMAI, Kiyoshi KATO, Yuto YAKUBO, Yuki HATA
  • Publication number: 20110176355
    Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 21, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuma Furutani, Yoshinori Ieda, Yuto Yakubo, Kiyoshi Kato, Shunpei Yamazaki
  • Publication number: 20110156023
    Abstract: In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 30, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshinori IEDA
  • Publication number: 20110114941
    Abstract: A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 19, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kiyoshi KATO, Yoshinori IEDA, Jun KOYAMA
  • Publication number: 20080315286
    Abstract: A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate. The first insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 25, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshinori IEDA