Patents by Inventor Yoshinori Muramatsu

Yoshinori Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120268630
    Abstract: A solid-state imaging device includes: a pixel array unit having plural pixels arranged in a row direction and a column direction; a weighted addition unit performing weighted addition on pixel signals read out from the plural pixels as analog signals; an A/D converter performing A/D conversion of the pixel signals on which weighted addition is performed; and a computing unit computing the A/D converted pixel signals.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 25, 2012
    Applicant: SONY CORPORATION
    Inventors: Ryo Ueda, Yoshinori Muramatsu, Atsushi Suzuki
  • Patent number: 8072521
    Abstract: A solid state imaging device with pixels in a two-dimensional array, a controller which performs window cutting on signals read out of the pixel array in multiple column units on a column-address basis, and a selector which, when the cutting window overlaps with a multiple column unit, holds signals in a present multiple column unit and in a previous column unit, and then outputs selected consecutive signals.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: December 6, 2011
    Assignee: Sony Corporation
    Inventors: Akihiko Kato, Tadayuki Taura, Yoshinori Muramatsu
  • Publication number: 20110221619
    Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicant: SONY CORPORATION
    Inventors: Go ASAYAMA, Noriyuki FUKUSHIMA, Yoshikazu NITTA, Yoshinori MURAMATSU, Kiyotaka AMANO
  • Publication number: 20110205097
    Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: SONY CORPORATION
    Inventors: Go ASAYAMA, Noriyuki FUKUSHIMA, Yoshikazu NITTA, Yoshinori MURAMATSU, Kiyotaka AMANO
  • Publication number: 20110199526
    Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Applicant: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiko Yasui
  • Patent number: 7993179
    Abstract: An exposure method that suppresses distribution of pattern shapes at the time of exposure. In a manufacturing method for a display unit, a layer forming a reference for pattern arrangement is determined among layers formed on a panel. An arrangement of a pattern in a layer above the reference layer is determined using a value obtained from distribution of the pattern arrangement in the reference layer.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Seiji Ishikawa, Jun Ooida, Yoshinori Muramatsu, Takahiro Miyazaki
  • Patent number: 7961238
    Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: June 14, 2011
    Assignee: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiko Yasui
  • Patent number: 7948415
    Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: May 24, 2011
    Assignee: Sony Corporation
    Inventors: Go Asayama, Noriyuki Fukushima, Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano
  • Patent number: 7936294
    Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: May 3, 2011
    Assignee: Sony Corporation
    Inventors: Go Asayama, Noriyuki Fukushima, Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano
  • Patent number: 7897969
    Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata
  • Patent number: 7880786
    Abstract: A CMOS color image sensor, which is a solid-state image pickup device, includes a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, each of the plurality of pixels converting the incident light intensity into an electrical signal; a pixel array including the plurality of pixels; row-selection lines; and column-reading lines. Two column-reading lines are provided for each column of the pixel array. Pixels in even rows of each column are connected to one column-reading line and pixels in odd rows of each column are connected to the other column-reading line.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: February 1, 2011
    Assignee: Sony Corporation
    Inventor: Yoshinori Muramatsu
  • Patent number: 7864237
    Abstract: A solid-state imaging device includes: a plurality of pixels each converting the amount of incident light into an electric signal and disposed in a plurality of columns to be deviated from the neighboring pixels in a row direction or in a column direction; a plurality of analog-to-digital converting units each converting an analog signal obtained from a corresponding pixel into a digital signal and disposed along a column in parallel; a plurality of column signal lines outputting the analog signals of the pixels of each of the plurality of pixel columns, disposed along the pixel columns, and making pairs; and a plurality of switching circuit units each selecting one column signal line of a corresponding pair of column signal lines. In the solid-state imaging device, the analog-to-digital converting units are connected to the output sides of the switching circuit units.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: January 4, 2011
    Assignee: Sony Corporation
    Inventor: Yoshinori Muramatsu
  • Patent number: 7859447
    Abstract: An image processing method for obtaining digital data comprising the steps of obtaining a plurality of image signals under a condition of different accumulation periods as an initial value for a counting operation, comparing, by using digital data for a first image signal of the plurality of image signals, an electric signal corresponding to a second image signal of the plurality of image signals with a reference signal, obtaining digital data for the second image signal, performing a counting operation in a mode having the same sign as the sign of digital data for the first image signal between a down-counting mode and an up-counting mode while the comparing step is being performed, and storing a count value.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: December 28, 2010
    Assignee: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiro Yasui
  • Publication number: 20100322506
    Abstract: An inspection system is disclosed, which inspects a wiring pattern on a high multilayer printed wiring board while determining a calibration position with a smaller number of error reports, and predicts the verification work time by evaluating the inspection property. Based on the CAD data of each layer of the printed wiring board to be inspected and the layer structure information, an intensity composition map viewed through the inspection surface is generated. A plurality of sets of the intensity components of the inspection surface are determined, and after determining at least one intensity evaluation region covering all the sets, the intensity evaluation region is imaged by an inspection unit and the statistical intensity value corresponding to each intensity component is determined and substituted into the intensity composition map. The inspection is conducted by determining the optimal calibration position for determining an inspection threshold value in this way.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 23, 2010
    Inventors: Yoshinori MURAMATSU, Ryoji Shiwaku, Tadashi Iida
  • Publication number: 20100245649
    Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.
    Type: Application
    Filed: May 3, 2010
    Publication date: September 30, 2010
    Applicant: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiko Yasui
  • Patent number: 7804535
    Abstract: In a solid-state imaging device meeting color image pickup, which an AD converter is mounted on the same chip, the circuit scale and the number of transmission signal lines are reduced and a reference signal suitable for color image pickup is fed to an AD conversion comparing portion. DA converter circuits for two pixels of a repeat unit of a separation filter in the horizontal row direction in a unit of readout are prepared as a functional portion to generate a reference signal for AD conversion. The DA converter circuits generate the reference signals having a tilt in accordance with a color property and varying from an initial value based on a non-color property such as a black reference and a circuit offset. Each reference signal independently outputted from the DA converter circuits is basically directly transmitted through common signal lines to a voltage comparing portion which corresponds to color filters having a common color property through independent signal lines.
    Type: Grant
    Filed: April 30, 2005
    Date of Patent: September 28, 2010
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Noriyuki Fukushima, Yoshikazu Nitta, Yukihiro Yasui
  • Patent number: 7800526
    Abstract: A data processing apparatus and method is disclosed for obtaining digital data for a plurality of signals to be processed, comprising. The disclosed process includes comparing, by using digital data for a first signal of the plurality of signals, an electric signal corresponding to a second signal of the plurality of signals with a reference signal; obtaining digital data for the second signal based on the comparing step; performing a counting operation in one of a down-counting mode and an up-counting mode while the comparing step is being performed; storing a first count value; outputting the first count value as computed data at a predetermined time; generating normal data based on one of the plurality of signals to be processed; and outputting the normal data.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: September 21, 2010
    Assignee: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiro Yasui
  • Patent number: 7786921
    Abstract: In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: August 31, 2010
    Assignee: Sony Corporation
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiro Yasui
  • Patent number: 7750836
    Abstract: A solid-state imaging device including: an analog-digital converter unit in column parallel arrangement, the analog-digital converter unit having a plurality of pixels arranged to convert an incident light quantity to an electric signal, in which an analog signal obtained from the pixel is converted into a digital signal, wherein the analog-digital converter unit is configured of: a comparator operable to compare a value of a column signal line from which an analog signal obtained by the pixel is outputted with a value of a reference line, and a counter operable to measure a time period by the time when comparison done by the comparator is finished and to store the comparison result, wherein the solid-state imaging device further includes: a module for controlling an output of the comparator operable to control the output of the comparator depending on the output of the comparator.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: July 6, 2010
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Kiyotaka Amano, Atsushi Suzuki, Noriyuki Fukushima
  • Publication number: 20100165164
    Abstract: A negative electrode for a secondary battery includes a negative electrode current collector and a negative electrode active material layer provided in the negative electrode current collector and which is alloyed with the negative electrode current collector at least at a part of an boundary face between it and the negative electrode current collector, wherein the negative electrode current collector has a first surface on which the negative electrode active material layer is formed and a second surface on which the negative electrode active material layer is not formed, the negative electrode having a portion in which the second surfaces of the negative electrode current collector are opposed to each other.
    Type: Application
    Filed: March 11, 2010
    Publication date: July 1, 2010
    Applicant: Sony Corporation
    Inventor: Yoshinori Muramatsu