Patents by Inventor Yoshinori Takenaka

Yoshinori Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010796
    Abstract: A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 ?m or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: June 11, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshinori Takenaka
  • Patent number: 11715698
    Abstract: A wiring substrate includes a core substrate, and a build-up part formed on the core substrate and including insulating layers and conductor layers. The conductor layers include one or more conductor layers each having a first wiring and a second wiring such that the second wiring has a conductor thickness smaller than a conductor thickness of the first wiring and that a minimum value of a line width of a wiring pattern of the second wiring is smaller than a minimum value of a line width of a wiring pattern of the first wiring.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: August 1, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Tomoyuki Ikeda, Yoshinori Takenaka
  • Publication number: 20230011786
    Abstract: A wiring substrate includes an insulating layer including resin and filler particles, and an embedded wiring layer including wirings and embedded in the insulating layer such that the wirings are filling grooves formed on a surface of the insulating layer, respectively. The embedded wiring layer is formed such that the smallest line width of the wirings in the embedded wiring layer is in the range of 2 ?m to 8 ?m, and the insulating layer is formed such that the maximum particle size of the filler particles is 50% or less of the smallest line width of the wirings in the embedded wiring layer.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 12, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Yoshinori TAKENAKA
  • Publication number: 20230008582
    Abstract: A wiring substrate includes an insulating layer including resin and filler particles, and an embedded wiring layer including wirings and embedded in the insulating layer such that the wirings are filling grooves formed on a surface of the insulating layer, respectively. The embedded wiring layer is formed such that the inter-wiring distance between the closest two wirings of the wirings in the embedded wiring layer is in the range of 2 ?m to 8 ?m, and the insulating layer is formed such that the maximum particle size of the filler particles is 50% or less of the inter-wiring distance.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 12, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Yoshinori TAKENAKA
  • Publication number: 20220386461
    Abstract: A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 ?m or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 1, 2022
    Applicant: IBIDEN CO., LTD.
    Inventor: Yoshinori TAKENAKA
  • Publication number: 20220223532
    Abstract: A wiring substrate includes a core substrate, and a build-up part formed on the core substrate and including insulating layers and conductor layers. The conductor layers include one or more conductor layers each having a first wiring and a second wiring such that the second wiring has a conductor thickness smaller than a conductor thickness of the first wiring and that a minimum value of a line width of a wiring pattern of the second wiring is smaller than a minimum value of a line width of a wiring pattern of the first wiring.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 14, 2022
    Applicant: IBIDEN CO., LTD.
    Inventors: Tomoyuki IKEDA, Yoshinori TAKENAKA
  • Patent number: 10271426
    Abstract: A printed wiring board includes a first conductor layer including a first conductor circuit and a second conductor circuit formed adjacent to the first conductor circuit, a resin insulating layer formed on the first conductor layer such that the insulating layer is filling space between the first and second conductor circuits, and a second conductor layer formed on the insulating layer such that the insulating layer is interposed between the first and second conductor layers. The first conductor layer has thickness in the range of 1 ?m to 15 ?m and is formed such that the space between the first and second conductor circuits has width in the range of 2 ?m to 7 ?m, and the insulating layer includes inorganic particles having average particle diameter in the range of 0.05 ?m to 1.0 ?m and content in the range of 35 wt. % to 75 wt. % in the insulating layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 23, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyasu Noto, Yoshinori Takenaka
  • Patent number: 10271427
    Abstract: A printed wiring board includes a first conductor layer including a first conductor circuit and a second conductor circuit formed adjacent to the first circuit, a resin insulating layer formed on the first conductor layer such that the insulating layer is filling space between the first and second conductor circuits, and a second conductor layer formed on the insulating layer such that distance (T) between the first and second conductor layers is in the range of 4.5 ?m to 10.5 ?m. The resin insulating layer includes inorganic particles having average particle diameter (D1) such that ratio (D1/S) of the diameter (D1) to distance (S) of the space is less than 0.25 and that ratio (D1/T) of the diameter (D1) to the distance (T) is less than 0.25, where the distance (S) of the space between the first and second conductor circuits is in the range of 4.5 ?m to 10.5.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 23, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyasu Noto, Yoshinori Takenaka
  • Patent number: 10070511
    Abstract: A wiring board includes an insulating resin layer including resin material and filler, and a conductive circuit layer laminated on a surface of the insulating resin layer and having wiring patterns. The filler has particle diameters of 15% or less of a minimum width of the wiring patterns when the particle diameters of the filler is measured in a unit range defined such that the unit range has a width and a length where the length is measured from the surface of the insulating resin layer and is selected from a smaller of twice the minimum width of the wiring patterns and a plate thickness of the insulating resin layer, and the width is twice the minimum width of the wiring patterns.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshinori Takenaka, Hiroyasu Noto
  • Publication number: 20180213644
    Abstract: A printed wiring board includes an interlayer resin insulating layer including resin and inorganic particles, a via conductor formed through the insulating layer, a first conductor layer formed on the first surface of the insulating layer and including a land portion of the via conductor on the first surface, and a second conductor layer formed on second surface of the insulating layer and connected to bottom of the via conductor. The bottom of the via conductor has diameter of 20 to 35 ?m, the first conductor layer has thickness of 3 to 12 ?m, the insulating layer has thickness of 1 to 15 ?m, the second conductor layer has thickness of 1 to 12 ?m, and the second conductor and insulating layers are formed such that T1/T2 is 0.06 to 7.00 where T1 represents the thickness of the second conductor layer, and T2 represents the thickness of the insulating layer.
    Type: Application
    Filed: January 26, 2018
    Publication date: July 26, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Hiroyasu Noto, Yoshinori Takenaka
  • Publication number: 20180084641
    Abstract: A printed wiring board includes a first conductor layer including a first conductor circuit and a second conductor circuit formed adjacent to the first circuit, a resin insulating layer formed on the first conductor layer such that the insulating layer is filling space between the first and second conductor circuits, and a second conductor layer formed on the insulating layer such that distance (T) between the first and second conductor layers is in the range of 4.5 ?m to 10.5 ?m. The resin insulating layer includes inorganic particles having average particle diameter (D1) such that ratio (D1/S) of the diameter (D1) to distance (S) of the space is less than 0.25 and that ratio (D1/T) of the diameter (D1) to the distance (T) is less than 0.25, where the distance (S) of the space between the first and second conductor circuits is in the range of 4.5 ?m to 10.5.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 22, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Hiroyasu NOTO, Yoshinori TAKENAKA
  • Publication number: 20180084640
    Abstract: A printed wiring board includes a first conductor layer including a first conductor circuit and a second conductor circuit formed adjacent to the first conductor circuit, a resin insulating layer formed on the first conductor layer such that the insulating layer is filling space between the first and second conductor circuits, and a second conductor layer formed on the insulating layer such that the insulating layer is interposed between the first and second conductor layers. The first conductor layer has thickness in the range of 1 ?m to 15 ?m and is formed such that the space between the first and second conductor circuits has width in the range of 2 ?m to 7 ?m, and the insulating layer includes inorganic particles having average particle diameter in the range of 0.05 ?m to 1.0 ?m and content in the range of 35 wt. % to 75 wt. % in the insulating layer.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 22, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Hiroyasu NOTO, Yoshinori TAKENAKA
  • Publication number: 20180054885
    Abstract: A wiring board includes an insulating resin layer including resin material and filler, and a conductive circuit layer laminated on a surface of the insulating resin layer and having wiring patterns. The filler has particle diameters of 15% or less of a minimum width of the wiring patterns when the particle diameters of the filler is measured in a unit range defined such that the unit range has a width and a length where the length is measured from the surface of the insulating resin layer and is selected from a smaller of twice the minimum width of the wiring patterns and a plate thickness of the insulating resin layer, and the width is twice the minimum width of the wiring patterns.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 22, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoshinori TAKENAKA, Hiroyasu NOTO
  • Patent number: 9888581
    Abstract: A method for manufacturing a wiring board includes preparing a core structure, forming on a first surface of the core structure a first buildup structure including insulation layers, and forming on a second surface of the core structure on the opposite side of the first surface of the core structure a second buildup structure including insulation layers and an inductor device. The insulation layers in the second buildup structure have thicknesses which are thinner than thicknesses of the insulation layers in the first buildup structure, and the forming of the second buildup structure includes forming the inductor device in the second buildup structure on the second surface of the core structure such that at least a portion of a conductive pattern formed in the core structure is included as a portion of the inductor device.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 6, 2018
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshinori Takenaka
  • Publication number: 20150319866
    Abstract: A wiring board includes a core structure having a first surface and a second surface on the opposite side of the first surface, a first buildup structure formed on the first surface of the core structure and including insulation layers, and a second buildup structure formed on the second surface of the core structure and including insulation layers and an inductor device. The insulation layers in the second buildup structure have the thicknesses which are thinner than the thicknesses of the insulation layers in the first buildup structure, and the inductor device in the second buildup structure is position on the second surface of the core structure and includes at least a portion of a conductive pattern formed in the core structure.
    Type: Application
    Filed: July 9, 2015
    Publication date: November 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventor: Yoshinori TAKENAKA
  • Patent number: 9113569
    Abstract: A wiring board includes a core structure having a first surface and a second surface on the opposite side of the first surface, a first buildup structure formed on the first surface of the core structure and including insulation layers, and a second buildup structure formed on the second surface of the core structure and including insulation layers and an inductor device. The insulation layers in the second buildup structure have the thicknesses which are thinner than the thicknesses of the insulation layers in the first buildup structure, and the inductor device in the second buildup structure is position on the second surface of the core structure and includes at least a portion of a conductive pattern formed in the core structure.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 18, 2015
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshinori Takenaka
  • Patent number: 8993894
    Abstract: A printed wiring board includes a core substrate having first and second surfaces, a first conductor formed on the first surface of the substrate, a second conductor formed on the second surface of the substrate, a first through-hole conductor formed through the substrate and connecting the first and second conductors, and a second through-hole conductor formed through the substrate and connecting the first and second conductors. The second through-hole conductor has a diameter which is greater than a diameter of the first through-hole conductor, the first through-hole conductor has a roughened inner wall forming an interior space, the second through-hole conductor has a roughened inner wall forming an interior space, and the roughened inner wall of the first through-hole conductor has an arithmetic average roughness which is set lower than an arithmetic average roughness of the roughened inner wall of the second through-hole conductor.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Hideyuki Kawai, Yoshinori Takenaka
  • Patent number: 8853552
    Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: October 7, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshinori Takenaka, Takeshi Nakamura
  • Publication number: 20140116769
    Abstract: A printed wiring board including an insulative material, a first conductive circuit formed on the insulative material, a resin insulation layer including a first insulation layer formed on the insulative material and on the first conductive circuit and which insulates between lines of the first conductive circuit, the first insulation layer including inorganic particles having a first average diameter, and a second insulation layer formed on the first insulation layer and including a recessed portion and an opening portion, the second insulation layer including inorganic particles having a second average diameter smaller than the first average diameter, a second conductive circuit formed in the recessed portion, and a via conductor formed in the opening portion and which connects the first conductive circuit to the second conductive circuit.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoshinori TAKENAKA, TAKESHI NAKAMURA, TAKAMITSU HATTORI
  • Publication number: 20120314389
    Abstract: A wiring board has a core structure having a first surface and a second surface on the opposite side of the first surface of the core structure, a first buildup structure formed on the first surface of the core structure and having insulation layers and conductive layers, and a second buildup structure formed on the second surface of the core structure and having insulation layers, conductive layers and an inductor device. The conductive layers in the second buildup structure include conductive patterns forming the inductor device, and one or more of the conductive patterns forming the inductor device has the thickness which is greater than the thicknesses of the conductive layers in the first buildup structure.
    Type: Application
    Filed: March 20, 2012
    Publication date: December 13, 2012
    Applicant: IBIDEN CO., LTD.
    Inventor: Yoshinori TAKENAKA