Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Abstract: A method includes: an input step of inputting boundary surface information 11 on an object to a computer using the computer; a grid sampling step of determining cutting points 13 where the boundary surface cuts across edges of a predetermined rectangular parallelepiped grid 12 and normal vectors 14 of the boundary surface at the cutting points, and storing them in a storage unit as primary data 15; a D-polyhedron data generation step of connecting adjacent cutting points with a line segment to form a triangle one by one for generating D-polyhedron data 16 constituted of triangles only; and a V-polyhedron data generation step of generating V-polyhedron data 17 constituted of intersections of a plurality of infinite planes passing through the cutting points and whose normals coincide with the normal vectors. Any one of the D-polyhedron data and the V-polyhedron data is generated from the primary data 15, and the other is generated as a dual.

Abstract: A cutting point calculation step defines the cell complex that contains the boundary data, and calculating a cutting point where the boundary data cuts an edge or vertex of the rectangular parallelepiped cell of the cell complex. A cycle formation step classifies the rectangular parallelepiped cells into a boundary cell having the cutting point and a nonboundary cell having no cutting point, acquiring a cutting segment between a cell surface and boundary data for each boundary cell, and forming a cutting segment cycle closed by connecting the cutting points and the cutting segments alternately in sequence. A cycle internal division step divides the inside of the cutting segment cycle into cycle inner triangles sharing an adjacent side, for each boundary cell. A simplification step of unifying a plurality of cutting points on each edge, and registering the cycle inner triangles in the cell, for each boundary cell.

Abstract: By external data acquisition means using a computer, external data comprised of boundary data for an object is obtained; by external data input means, the external data are inputted into the computer; by cell dividing means, the external data are divided to rectangular parallelepiped cells that boundary planes intersect perpendicularly; by cell sorting means, the individual cells are sorted into boundary cells that include boundary data and non-boundary cells that do not include boundary data; by space sorting means, respective spaces are assigned to different space numbers where the cells are partitioned according to the boundary data; and by space number compression means, adjacent cells are reassigned to the same space numbers for cells that are not partitioned according to the boundary data.

Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Abstract: In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.

Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.

Abstract: A method includes: an input step of inputting boundary surface information 11 on an object to a computer using the computer; a grid sampling step of determining cutting points 13 where the boundary surface cuts across edges of a predetermined rectangular parallelepiped grid 12 and normal vectors 14 of the boundary surface at the cutting points, and storing them in a storage unit as primary data 15; a D-polyhedron data generation step of connecting adjacent cutting points with a line segment to form a triangle one by one for generating D-polyhedron data 16 constituted of triangles only; and a V-polyhedron data generation step of generating V-polyhedron data 17 constituted of intersections of a plurality of infinite planes passing through the cutting points and whose normals coincide with the normal vectors. Any one of the D-polyhedron data and the V-polyhedron data is generated from the primary data 15, and the other is generated as a dual.

Abstract: A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A RISC type of CPU is provided to execute an object program in which a stack area is used. The CPU is configured to have a return instruction based on an operand at which an open size is specified and to perform the return instruction when the stack area is required to be opened in returning processing executed by the CPU from interrupt processing to ordinary processing with no interrupt. Also a compiler is provided to compile a source program into the object program. The compiler determines whether or not a stack area in the source program is required to be opened when processing in the source program is returned from interrupt processing to ordinary processing with no interrupt and produces codes of the object program in which an operand for a return instruction is included and an open size for the stack area is specified at the operand.

Abstract: In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.

Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.

Abstract: A method of converting three-dimensional shape data into cell internal data. The method includes an oct-tree division step of dividing external data including boundary data of a target object into rectangular parallelepiped cells having boundary planes orthogonal to each other by oct-tree division. The method further includes a cell classification step of classifying each of the cells into an internal cell positioned inside or outside the target object or a boundary cell including the boundary data, and a cut point determination step of determining cut points of edges of the boundary cell based on the boundary data. The method further includes a boundary surface determination step of connecting cut points to form a polygon, and determining the polygon as the cell internal data when the number of the determined cut points is no fewer than 3 and no more than 12.

Abstract: A method and a program for converting boundary data into cell inner shape data, includes a division step (A) of dividing external data (12) constituted of the boundary data of an object into cells (13) in an orthogonal grid, a cutting point deciding step (B) of deciding an intersection point of the boundary data and a cell edge as a cell edge cutting point, a boundary deciding step (C) of deciding a boundary formed by connecting the cell edge cutting points as the cell inner shape data, a cell classification step (D) of classifying the divided cells into a nonboundary cell (13a) including no boundary surface and a boundary cell (13b) including a boundary surface, and a boundary cell data classification step (E) of classifying cell data constituting the boundary cell into internal cell data inside the cell inner shape data and external cell data outside the cell inner shape data.

Abstract: By external data acquisition means using a computer, external data comprised of boundary data for an object is obtained; by external data input means, the external data are inputed into the computer; by cell dividing means, the external data are divided to rectangular parallelepiped cells that boundary planes intersect perpendicularly; by cell sorting means, the individual cells are sorted into boundary cells that include boundary data and non-boundary cells that do not include boundary data; by space sorting means, respective spaces are assigned to different space numbers where the cells are partitioned according to the boundary data; and by space number compression means, adjacent cells are reassigned to the same space numbers for cells that are not partitioned according to the boundary data.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a CPU identification register which stores an identification value for identifying the corresponding CPU. When a program which is specific to a CPU is to be executed by that CPU, the corresponding identification value is read out from the identification register of the CPU and is judged, and branching to the appropriate program is performed based on the judgement result.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.