Abstract: A semiconductor device 2 has a plurality of elements. It also has an F-V table storing unit for low voltage threshold cells 31 for storing an F-V table TB11 of an oscillation frequency f1 relying on the plurality of elements and a power supply voltage EV to be supplied to the plurality of elements. It has a process sensor block 12 having at least one of the plurality of elements, for monitoring the oscillation frequency f1 relying on at least one element. It further has a selector 33 for setting the power supply voltage EV associated with the oscillation frequency f1, as the supply voltage to be supplied to the semiconductor device 2 by selecting according to the F-V table TB11. The F-V table TB11 is obtained by mutually relating the combinations of random number models ?n between an F-? table TB20 and an ?-V table TB30.

Abstract: A computer-readable recording medium stores a design support program causing a computer to perform: detecting a data path and a clock path corresponding to the data path making up a partial circuit in a circuit-under-design; selecting an object cell from cells on the data path and the clock path detected in the detecting; replacing the object cell selected in the selecting with a cell having a function substantially identical to and characteristics different from the object cell; acquiring a plurality of types of characteristic information related to the partial circuit based on the data path and the clock path after the object cell is replaced in the replacing; determining whether the types of the characteristic information acquired in the acquiring is in violation of restrictions; and outputting a determination result determined in the determining.

Abstract: A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.

Abstract: A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.

Abstract: A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans.

Abstract: A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling a first power supply line and the second power supply line and the contact resistance value.

Abstract: A semiconductor device 2 has a plurality of elements. It also has an F-V table storing unit for low voltage threshold cells 31 for storing an F-V table TB11 of an oscillation frequency f1 relying on the plurality of elements and a power supply voltage EV to be supplied to the plurality of elements. It has a process sensor block 12 having at least one of the plurality of elements, for monitoring the oscillation frequency f1 relying on at least one element. It further has a selector 33 for setting the power supply voltage EV associated with the oscillation frequency f1, as the supply voltage to be supplied to the semiconductor device 2 by selecting according to the F-V table TB11. The F-V table TB11 is obtained by mutually relating the combinations of random number models ?n between an F-? table TB20 and an ?-V table TB30.

Abstract: A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans.

Abstract: The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient ?, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S.

Abstract: The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient ?, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S.

Abstract: A biodegradable sheet or film that is excellent in environmental compatibility accompanied by less time dependent alteration following manufacture of the sheet, having stable flexibility is provided, which can be degraded by a microorganism or the like, and thus can be easily disposed after use. A biodegradable resin sheet which is constituted with a biodegradable (3-HA) copolymer, wherein the rate of change of the tensile elongation with respect to the change in crystallinity (%) from day 1 to day 30 after manufacturing the sheet represented by the formula (1): {[(tensile elongation (%) after a lapse of 1 day following manufacture)?(tensile elongation (%) after a lapse of 30 days following manufacture)]/[(crystallinity (%) after a lapse of 30 days following manufacture)?(crystallinity (%) after a lapse of 1 day following manufacture)]} is equal to or less than 20, and the tensile elongation after a lapse of 60 days following manufacture of the sheet is equal to or greater than 100(%).

Abstract: A method is realized for easily performing, without using a masking tape, an operation to accurately form a coating film 31 only on a coated section (?8) partly formed on the surface of a hub main body 13a. The upper end face of a rubber closed end cylindrical masking cover 32 is elastically pressed against the outside end surface of a cylindrical section 16 forming the hub main body 13a. As a result a border section between the coated section (?8) and the portion adjacent to the coated section (?8) can be made liquid-tight. In this state, coating particles are electrodeposited on the coated section (?8) by bringing a coating liquid 28 discharged from a liquid supply tube 29 into contact with the coated section (?8). By adopting such a method, the problems can be solved.

Abstract: A material for an organic electroluminescence element, characterized in that it comprises a platinum complex formed from a platinum ion and a ligand having at least one aryl group being not capable of free rotation or at least one aromatic heterocyclic group being not capable of free rotation; a display device, characterized in that it comprises said material for an organic electroluminescence element and exhibits high luminous efficiency and long luminous life; and an illumination device, characterized in that it comprises said material for an organic electroluminescence element and exhibits high luminous efficiency and long luminous life.

Abstract: A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

Abstract: A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

Abstract: A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.

Abstract: A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.

Abstract: A conveyor unit (2) including a driving roller (5), a motor (30) for powering the driving roller (5), and a controller (10) adapted to adjust the motor (30) so as to control the driving roller (5), the motor (30) including a permanent magnet and an armature having a plurality of armature coils (32a–32c), and the controller (10) having an interrupter (15) adapted to repeat shunting and deshunting of at least one of the coils (32a–32c) and a rotation detector (17) adapted to detect an externally forced rotation of the motor (30) in response to an electromotive force induced in at least one of the coils (32a–32c), wherein in the case that the motor (30) is not driven, the controller (10) maintains operations of the interrupter (15) and outputs a presence signal by determining conveyance of an article (W) into an area powered by the motor (30) upon detection of the rotation of the motor (30) by means of the rotation detector (17).

Abstract: A conveyor unit (2) including a driving roller (5), a motor (30) for powering the driving roller (5), and a controller (10) adapted to adjust the motor (30) so as to control the driving roller (5), the motor (30) including a permanent magnet and an armature having a plurality of armature coils (32a-32c), and the controller (10) having an interrupter (15) adapted to repeat shunting and deshunting of at least one of the coils (32a-32c) and a rotation detector (17) adapted to detect an externally forced rotation of the motor (30) in response to an electromotive force induced in at least one of the coils (32a-32c), wherein in the case that the motor (30) is not driven, the controller (10) maintains operations of the interrupter (15) and outputs a presence signal by determining conveyance of an article (W) into an area powered by the motor (30) upon detection of the rotation of the motor (30) by means of the rotation detector (17).

Abstract: An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.