Patents by Inventor Yoshio Mori

Yoshio Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230396181
    Abstract: A power conversion device includes a power converter including a semiconductor module, to convert input power and output the converted power, and a capacitor electrically connected to the semiconductor module. The capacitor includes a capacitor-side terminal surface on which a capacitor-side terminal is arranged, and the capacitor-side terminal surface faces a module-side terminal surface of the semiconductor module.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 7, 2023
    Inventors: Yuki YANO, Hiroyuki KUWAHARA, Yoshio MORI, Masamitsu TAKIZAWA, Jun KANDA
  • Publication number: 20220243093
    Abstract: Provided is a polishing composition that can reduce the friction force against an object to be polished while maintaining a favorable polishing removal rate. The polishing composition provided by the present invention contains water, an abrasive, and a composite metal oxide as an oxidant. The polishing composition further contains an anionic polymer. In some preferred embodiments, the polishing composition contains a permanganate as the composite metal oxide. The polishing composition is suitable for polishing a material having a Vickers hardness of 1500 Hv or higher.
    Type: Application
    Filed: June 15, 2020
    Publication date: August 4, 2022
    Inventors: Yasuaki ITO, Shinichiro TAKAMI, Yoshio MORI
  • Patent number: 10745588
    Abstract: This invention provides a silicon wafer polishing composition used in the presence of an abrasive. The composition comprises a silicon wafer polishing accelerator, an amide group-containing polymer, and water. The amide group-containing polymer has a building unit A in its main chain. The building unit A comprises a main chain carbon atom constituting the main chain of the amide group-containing polymer and a secondary amide group or a tertiary amide group. The carbonyl carbon atom constituting the secondary amide group or tertiary amide group is directly coupled to the main chain carbon atom.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 18, 2020
    Assignees: FUJIMI INCORPORATED, TOAGOSEI CO., LTD.
    Inventors: Kohsuke Tsuchiya, Hisanori Tansho, Taiki Ichitsubo, Yoshio Mori
  • Patent number: 10453770
    Abstract: In each of a plurality of semiconductor element groups of a power converter, a second semiconductor switching element and a third semiconductor switching element are shifted from each other in a second direction such that at least a portion of fins with which the second semiconductor switching element overlaps as viewed in a direction orthogonal to surfaces of coolers is different from fins with which the third semiconductor switching element overlaps as viewed in the direction orthogonal to the surfaces of the coolers.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masamitsu Takizawa, Nobuyuki Kobayashi, Yoshio Mori, So Nakamichi, Kohei Matsui
  • Publication number: 20190148259
    Abstract: In each of a plurality of semiconductor element groups of a power converter, a second semiconductor switching element and a third semiconductor switching element are shifted from each other in a second direction such that at least a portion of fins with which the second semiconductor switching element overlaps as viewed in a direction orthogonal to surfaces of coolers is different from fins with which the third semiconductor switching element overlaps as viewed in the direction orthogonal to the surfaces of the coolers.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 16, 2019
    Inventors: Masamitsu TAKIZAWA, Nobuyuki KOBAYASHI, Yoshio MORI, So NAKAMICHI, Kohei MATSUI
  • Patent number: 10227518
    Abstract: Provided is a polishing composition with which surface defects can be efficiently reduced. This invention provides a polishing composition comprising a water-soluble polymer MC-end. The main chain of the water-soluble polymer MC-end is formed with a non-cationic region as its main structural part and a cationic region located at least at one end of the main chain. The cationic region has at least one cationic group.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 12, 2019
    Assignee: FUJIMI INCORPORATED
    Inventors: Kohsuke Tsuchiya, Yoshio Mori
  • Patent number: 10224372
    Abstract: A method of forming a device includes forming an in-process alternating stack of insulating layers and sacrificial material layers over a substrate, forming sacrificial pillar structures through the in-process alternating stack, where the sacrificial pillar structures are arranged in rows, forming inter-pillar cavities between each neighboring pair of sacrificial pillar structures, forming dielectric bridge structures by depositing a dielectric fill material in the inter-pillar cavities, selectively removing the sacrificial pillar structures to form pillar cavities, replacing remaining portions of the sacrificial material layers with electrically conductive layers through the pillar cavities, and forming pillar structures in the pillar cavities, where each of the pillar structures includes a respective vertical electrode.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoshio Mori
  • Patent number: 10192929
    Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoshio Mori
  • Publication number: 20180342557
    Abstract: A method of forming a device includes forming an in-process alternating stack of insulating layers and sacrificial material layers over a substrate, forming sacrificial pillar structures through the in-process alternating stack, where the sacrificial pillar structures are arranged in rows, forming inter-pillar cavities between each neighboring pair of sacrificial pillar structures, forming dielectric bridge structures by depositing a dielectric fill material in the inter-pillar cavities, selectively removing the sacrificial pillar structures to form pillar cavities, replacing remaining portions of the sacrificial material layers with electrically conductive layers through the pillar cavities, and forming pillar structures in the pillar cavities, where each of the pillar structures includes a respective vertical electrode.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 29, 2018
    Inventor: Yoshio MORI
  • Publication number: 20180277596
    Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventor: Yoshio MORI
  • Patent number: 9944838
    Abstract: Provided is a polishing composition with which haze and surface defects can be reduced. This invention provides a polishing composition comprising a synthetic water-soluble polymer ML-end that has a hydrophobic region at least at one end of its main chain. The hydrophobic region has at least one hydrophobic group derived from a polymerization initiator.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 17, 2018
    Assignee: FUJIMI INCORPORATED
    Inventors: Kohsuke Tsuchiya, Yoshio Mori
  • Publication number: 20170253767
    Abstract: This invention provides a silicon wafer polishing composition used in the presence of an abrasive. The composition comprises a silicon wafer polishing accelerator, an amide group-containing polymer, and water. The amide group-containing polymer has a building unit A in its main chain. The building unit A comprises a main chain carbon atom constituting the main chain of the amide group-containing polymer and a secondary amide group or a tertiary amide group. The carbonyl carbon atom constituting the secondary amide group or tertiary amide group is directly coupled to the main chain carbon atom.
    Type: Application
    Filed: May 23, 2017
    Publication date: September 7, 2017
    Applicants: FUJIMI INCORPORATED, TOAGOSEI CO., LTD.
    Inventors: Kohsuke TSUCHIYA, Hisanori TANSHO, Taiki ICHITSUBO, Yoshio MORI
  • Patent number: 9685341
    Abstract: The polishing composition has a pH of 7 or more and is used in applications for polishing a silicon substrate. The polishing composition contains abrasive grains and a water-soluble polymer. The water-soluble polymer is a copolymer including a first monomer unit having a characteristic value P of 50-100 inclusive, and a second monomer unit having a characteristic value P of at least ?100 and less than 50. The characteristic value P is the result of subtracting an adsorption coefficient S2 of the abrasive grains obtained through a specific standard test B from a wettability coefficient S1 of the silicon substrate obtained through a specific standard test A.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 20, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Yoshio Mori, Kohsuke Tsuchiya, Maki Asada, Shuhei Takahashi
  • Patent number: 9579769
    Abstract: Provided is a polishing composition, which comprises abrasive grains, a water-soluble polymer, an aggregation inhibitor and water. The ratio R1/R2 is 1.3 or less, where R1 represents the average particle diameter of the particles present in the polishing composition and R2 represents the average particle diameter of the abrasive grains when the abrasive grains are dispersed in water at the same concentration as that of the abrasive grains in the polishing composition. The polishing composition can be used mainly for polishing the surface of a silicon substrate.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 28, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Kohsuke Tsuchiya, Yoshio Mori, Shinichiro Takami, Shuhei Takahashi
  • Patent number: 9530824
    Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Seje Takaki, Yoshio Mori
  • Publication number: 20160215189
    Abstract: Provided is a polishing composition with which surface defects can be efficiently reduced. This invention provides a polishing composition comprising a water-soluble polymer MC-end. The main chain of the water-soluble polymer MC-end is formed with a non-cationic region as its main structural part and a cationic region located at least at one end of the main chain. The cationic region has at least one cationic group.
    Type: Application
    Filed: September 22, 2014
    Publication date: July 28, 2016
    Applicant: FUJIMI INCORPORATED
    Inventors: Kohsuke TSUCHIYA, Yoshio MORI
  • Publication number: 20160215188
    Abstract: Provided is a polishing composition with which haze and surface defects can be reduced. This invention provides a polishing composition comprising a synthetic water-soluble polymer ML-end that has a hydrophobic region at least at one end of its main chain. The hydrophobic region has at least one hydrophobic group derived from a polymerization initiator.
    Type: Application
    Filed: September 22, 2014
    Publication date: July 28, 2016
    Applicant: FUJIMI INCORPORATED
    Inventors: Kohsuke TSUCHIYA, Yoshio MORI
  • Publication number: 20160141334
    Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Applicant: SANDISK 3D LLC
    Inventors: Seje Takaki, Yoshio Mori
  • Publication number: 20160122591
    Abstract: This invention provides a silicon wafer polishing composition used in the presence of an abrasive. The composition comprises a silicon wafer polishing accelerator, an amide group-containing polymer, and water. The amide group-containing polymer has a building unit A in its main chain. The building unit A comprises a main chain carbon atom constituting the main chain of the amide group-containing polymer and a secondary amide group or a tertiary amide group. The carbonyl carbon atom constituting the secondary amide group or tertiary amide group is directly coupled to the main chain carbon atom.
    Type: Application
    Filed: May 2, 2014
    Publication date: May 5, 2016
    Applicants: FUJIMI INCORPORATED, TOAGOSEI CO., LTD.
    Inventors: Kohsuke TSUCHIYA, Hisanori TANSHO, Taiki ICHITSUBO, Yoshio MORI
  • Patent number: 9252519
    Abstract: A metal plate contact has two slits running from an upper end towards a bottom wall. First and second trench for receiving trunk and branching cables, respectively, and a recess for mounting a contact that crosses these trenches are created in a middle portion in a lateral direction of a housing. Left and right movable ends are connected to the middle portion on the two sides in a longitudinal direction via a connection band. The movable ends can be folded towards the top of the middle portion. First and second upper side trenches for covering the top of the first trench and covering the top of the second trench, respectively, are created in these movable ends. A wire lid for positioning a cable end is formed in one end or in the two ends of the second trench or of the second upper side trench.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 2, 2016
    Assignee: NICHIFU TERMINAL INDUSTRIES CO., LTD.
    Inventors: Yoshio Mori, Yuji Nakajima