Patents by Inventor Yoshio Ozawa

Yoshio Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140070290
    Abstract: According to one embodiment, a ferroelectric memory includes a semiconductor layer, an interfacial insulating film formed on the semiconductor layer, a ferroelectric film formed on the interfacial insulating film, and a gate electrode formed on the ferroelectric film, wherein the ferroelectric film is a film which includes a metal that is hafnium (Hf) or zirconium (Zr) and oxygen as the main components and to which an element selected from the group consisting of silicon (Si), magnesium (Mg), aluminum (Al).
    Type: Application
    Filed: September 6, 2013
    Publication date: March 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji INUMIYA, Yoshio Ozawa, Koji Yamakawa, Atsuko Sakata, Masayuki Tanaka, Junichi Wada
  • Publication number: 20140070289
    Abstract: According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and oxygen, and contains an element other than the metal at a concentration lower than a concentration of the metal.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 13, 2014
    Inventors: Masayuki TANAKA, Junichi WADA, Yoshio OZAWA, Koji YAMAKAWA, Seiji INUMIYA, Atsuko SAKATA
  • Patent number: 8637915
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Publication number: 20140021430
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: September 27, 2013
    Publication date: January 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8618603
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Patent number: 8609487
    Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
  • Patent number: 8604536
    Abstract: A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8598561
    Abstract: A nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major surface and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face and has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that of the second major surface.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Ryota Fujitsuka, Yoshio Ozawa
  • Patent number: 8569728
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Publication number: 20130248808
    Abstract: A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noritake OOMACHI, Junichi WADA, Kouji MATSUO, Tomotaka ARIGA, Yoshio OZAWA
  • Publication number: 20130237008
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
    Type: Application
    Filed: April 25, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro NOJIRI, Hiroyuki FUKUMIZU, Shinichi NAKAO, Kei WATANABE, Kazuhiko YAMAMOTO, Ichiro MIZUSHIMA, Yoshio OZAWA
  • Patent number: 8530876
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8497184
    Abstract: In one embodiment, a method for manufacturing a semiconductor device includes forming a first conductor layer on a surface of a semiconductor layer via a tunnel insulating film. The method includes forming an isolation trench extending from a surface of the first conductor layer to the semiconductor layer to form a plurality of conductive plates on the tunnel insulating film. The method includes filling the isolation trench with an element insulation insulating film from bottom of the isolation trench to an intermediate portion of a side surface of each of the conductive plates. The method includes forming a silicon nitride film on an exposed surface of the each of the conductive plates not covered with the element insulation insulating film. In addition, the method includes filling an upper portion of the isolation trench by forming a second conductor layer above the conductive plates and the element insulation insulating film.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8455346
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shinichi Nakao, Kei Watanabe, Kazuhiko Yamamoto, Ichiro Mizushima, Yoshio Ozawa
  • Patent number: 8450715
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
  • Patent number: 8411486
    Abstract: According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Ryota Fujitsuka, Yoshio Ozawa
  • Patent number: 8404537
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20130055742
    Abstract: An equipment control system for equipment such as a refrigeration device, its control device, and its control program are provided in which defrosting operation start time can be changed appropriately. The integrated controller controls a defrosting operation to remove frost adhered to the equipment, in which the defrosting operation is started at a fixed or varying time interval. The integrated controller stores past data based on required time for past defrosting operations for different environmental conditions. The integrated controller includes an environmental condition acquisition unit for obtaining environmental conditions; a database control unit for obtaining required time for a defrosting operation based on the past record data corresponding to the present environmental conditions from the stored past data; and a start time changing unit for changing start time of the present-round defrosting operation based on the obtained required time.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Atsushi OUCHI, Yoshio OZAWA
  • Patent number: 8389968
    Abstract: According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: RE44630
    Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kai, Ryuji Ohba, Yoshio Ozawa