Patents by Inventor Yoshiro Shimojo

Yoshiro Shimojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12232325
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 18, 2025
    Assignee: KIOXIA CORPORATION
    Inventors: Keisuke Nakatsuka, Yoshitaka Kubota, Tetsuaki Utsumi, Yoshiro Shimojo, Ryota Katsumata
  • Patent number: 12211913
    Abstract: A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 28, 2025
    Assignee: Kioxia Corporation
    Inventor: Yoshiro Shimojo
  • Patent number: 12185539
    Abstract: In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 31, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuharu Yamabe, Yoshiro Shimojo
  • Publication number: 20240404920
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: August 16, 2024
    Publication date: December 5, 2024
    Applicant: Kioxia Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
  • Publication number: 20240407162
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: Kioxia Corporation
    Inventor: Yoshiro SHIMOJO
  • Publication number: 20240395697
    Abstract: A semiconductor device includes a substrate, plugs, and interconnections. The plugs include a first plug and a second plug that are disposed above the substrate and extend in a first direction that crosses an upper surface of the substrate, and a third plug disposed above and electrically connected to the second plug and extending in the first direction. The interconnections include a first interconnection disposed above and electrically connected to the first plug, a second interconnection disposed below and electrically connected to the first plug, and a third interconnection disposed below and electrically connected to the second plug. The first interconnection contains copper. The third plug contains tungsten. An upper end of the second plug is different in level from an upper end of the first plug and a lower end of the second plug is same in level as a lower end of the first plug.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 28, 2024
    Inventors: Mitsuhiko NODA, Masayoshi TAGAMI, Yoshiro SHIMOJO
  • Patent number: 12094805
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: September 17, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 12089404
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 10, 2024
    Assignee: Kioxia Corporation
    Inventor: Yoshiro Shimojo
  • Publication number: 20230114433
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Applicant: Kioxia Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro Shimojo, Shinya Arai
  • Patent number: 11552000
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Publication number: 20220285391
    Abstract: In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body.
    Type: Application
    Filed: August 26, 2021
    Publication date: September 8, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuharu YAMABE, Yoshiro SHIMOJO
  • Publication number: 20220278215
    Abstract: A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction.
    Type: Application
    Filed: August 23, 2021
    Publication date: September 1, 2022
    Inventor: Yoshiro SHIMOJO
  • Patent number: 11222900
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 11, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiro Shimojo, Tomoya Sanuki
  • Publication number: 20210399004
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke NAKATSUKA, Yoshitaka KUBOTA, Tetsuaki UTSUMI, Yoshiro SHIMOJO, Ryota KATSUMATA
  • Patent number: 11121147
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 14, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Yoshitaka Kubota, Tetsuaki Utsumi, Yoshiro Shimojo, Ryota Katsumata
  • Publication number: 20210159237
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiro SHIMOJO
  • Patent number: 10943914
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiro Shimojo
  • Publication number: 20210043546
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
  • Patent number: 10854534
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Publication number: 20200303395
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke NAKATSUKA, Yoshitaka KUBOTA, Tetsuaki UTSUMI, Yoshiro SHIMOJO, Ryota KATSUMATA