Patents by Inventor Yoshitaka Ito

Yoshitaka Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160074800
    Abstract: A honeycomb structure includes a honeycomb substrate having a porous partition wall that defines a plurality of cells that extend from an inlet end face as an inlet side for a fluid to an outlet end face as an outlet side for the fluid, and a porous circumferential wall that is monolithically formed with the partition wall, and a coat layer that is disposed on at least a part of the outer surface of the circumferential wall. Here, a part of the coat layer penetrates into the pores of the circumferential wall, and a thickness of the part of the coat layer that penetrates into the pores of the circumferential wall is from 1 to 90% of the thickness of the circumferential wall.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 17, 2016
    Inventors: Yoshitaka ITO, Hajime TANAKA
  • Publication number: 20150369885
    Abstract: A superconducting magnetic field generating device includes: a superconductor including an outer superconductor formed with a high temperature superconducting material in a cylindrical shape and generating a trapped magnetic field, and an inner superconductor formed with a high temperature superconducting material in a cylindrical shape and coaxially disposed with the outer superconductor on the inner circumferential side; and a cooling device cooling the outer and inner superconductors to a temperature equal to or lower than the superconducting transition temperature, wherein the inner superconductor is formed so that a ratio (Jc?1/Jcz1) of a critical current density (Jc?1) of the inner superconductor in the circumferential direction to a critical current density (Jcz1) of the inner superconductor in the axial direction is closer to 1 than a ratio (Jc?2/Jcz2) of the critical current density (Jc?2) in the circumferential direction to a critical current density (Jcz2) of the outer superconductor of the outer s
    Type: Application
    Filed: June 18, 2015
    Publication date: December 24, 2015
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Yoshitaka ITO, Yousuke YANAGI, Masaaki YOSHIKAWA
  • Publication number: 20150317258
    Abstract: A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Inventor: Yoshitaka ITO
  • Patent number: 9116840
    Abstract: A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshitaka Ito
  • Patent number: 9099794
    Abstract: Concave serrations are provided in an inner surface of a conductor crimping portion of a crimp terminal. A number of circular concave portions are provided in the inner surface of the conductor crimping portion as the concave serrations so as to be scattered in a state of being spaced aside from one another. A diameter of an inner bottom surface of each circular concave portion is set within a range of 0.15 (an error range is ±0.04) mm to 0.8 (the error range is ±0.04) mm. A serration angle between an extension surface of the inner bottom surface and an inner side surface of each circular concave portion is set within a range of 60 to 90 degrees. A shortest distance of a flat surface portion between peripheries of mutually adjacent circular concave portions is set to be 0.17 (the error range is ±0.09) mm.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: August 4, 2015
    Assignee: YAZAKI CORPORATION
    Inventors: Yoshitaka Ito, Takaya Kondou, Masanori Onuma
  • Patent number: 9099792
    Abstract: A crimping terminal includes a conductor crimping portion which is connected to an electric cable so as to crimp the electric cable. The conductor crimping portion includes a bottom plate on which a conductor is placed and a pair of conductor crimping tabs which is provided on both sides of the bottom plate. The conductor crimping portion includes serrations that are formed at least a part of the inner surface thereof and retains the conductor of the electric cable inside the conductor crimping portion and at least one bead that protrudes from the inner surface.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: August 4, 2015
    Assignee: Yazaki Corporation
    Inventors: Takaya Kondou, Masanori Onuma, Yoshitaka Ito
  • Publication number: 20150153970
    Abstract: A printing management apparatus includes a storage unit, a confirmation unit, a changing unit, and a processor. The storage unit stores schedule information including a correspondence among a visit schedule for a user to visit a visit destination, a printing schedule of target print data associated with the visit destination, and a printing location for the target print data. The confirmation unit confirms whether or not the visit schedule is to be changed, in accordance with a positional relationship between the visit destination and the user. When the visit schedule is changed, the changing unit changes the printing schedule in accordance with the change. The processor causes the target print data to be printed by using a printer installed in the printing location, in accordance with the printing schedule.
    Type: Application
    Filed: July 3, 2014
    Publication date: June 4, 2015
    Applicant: FUJI XEROX CO., LTD
    Inventors: Munenori TOMIDA, Yoshitaka ITO
  • Publication number: 20150106558
    Abstract: A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventor: Yoshitaka ITO
  • Publication number: 20150031734
    Abstract: Provided is a mirabegron-containing pharmaceutical composition in which the leakage of mirabegron can be inhibited when the pharmaceutical composition is dispersed in a liquid, and in which the change in pharmacokinetics caused by the presence or absence of food intake is decreased. The pharmaceutical composition comprises an acid addition salt of alkyl sulfuric acid and mirabegron, and a base for modified release.
    Type: Application
    Filed: March 29, 2013
    Publication date: January 29, 2015
    Inventors: Yuki Kasashima, Keiichi Yoshihara, Yoshitaka Ito, Takatsune Yoshida, Yumi Matsui
  • Patent number: 8918611
    Abstract: A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.
    Type: Grant
    Filed: March 13, 2011
    Date of Patent: December 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshitaka Ito
  • Publication number: 20140213123
    Abstract: Concave serrations are provided in an inner surface of a conductor crimping portion of a crimp terminal. A number of circular concave portions are provided in the inner surface of the conductor crimping portion as the concave serrations so as to be scattered in a state of being spaced aside from one another. A diameter of an inner bottom surface of each circular concave portion is set within a range of 0.15 (an error range is ±0.04) mm to 0.8 (the error range is ±0.04) mm. A serration angle between an extension surface of the inner bottom surface and an inner side surface of each circular concave portion is set within a range of 60 to 90 degrees. A shortest distance of a flat surface portion between peripheries of mutually adjacent circular concave portions is set to be 0.17 (the error range is ±0.09) mm.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Applicant: Yazaki Corporation
    Inventors: Yoshitaka ITO, Takaya KONDOU, Masanori ONUMA
  • Patent number: 8747169
    Abstract: A connector housing includes an upper housing having a front end wall that defines the front end of a terminal containing chamber, and a lower housing having an opening section due to the lack of a front end wall. The front end wall of the upper housing has an insertion hole. The lower housing has the terminal containing chamber, and is disposed with a lance which is formed by using the opening section on the front end of the lower housing as a through hole. The upper housing and the lower housing have restricting portions which inhibit the relative displacement of both housings in the front and back direction when united, and a locking mechanism for maintaining the united state by restricting the upper housing and lower housing from separating in the upper or lower direction.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Yazaki Corporation
    Inventor: Yoshitaka Ito
  • Publication number: 20140004759
    Abstract: A crimping terminal comprises: a conductor crimping portion including a bottom plate and a pair of conductor crimping tabs, the conductor crimping tabs being extending from both sides of the bottom plate in a widthwise direction perpendicular to a lengthwise direction of the crimping terminal and being configured to crimp a conductor of an electrical cable so as to wrap the conductor, the conductor being formed by a bundle of wires and serving as a crimping subject disposed on the bottom plate along the lengthwise direction, the inner surface of the conductor crimping portion being provided with serrations including a plurality of uniformly cylindrical recesses with a diameter smaller than the diameter of the wire of the conductor, and wherein, in the plurality of recesses, the adjacent recesses deviated from each other in the widthwise direction of the crimping terminal partly overlap each other when seen from the lengthwise direction.
    Type: Application
    Filed: February 1, 2012
    Publication date: January 2, 2014
    Applicant: YAZAKI CORPORATION
    Inventors: Takaya Kondou, Masanori Onuma, Yoshitaka Ito
  • Publication number: 20140004758
    Abstract: A crimping terminal includes a conductor crimping portion which is connected to an electric cable so as to crimp the electric cable. The conductor crimping portion includes a bottom plate on which a conductor is placed and a pair of conductor crimping tabs which is provided on both sides of the bottom plate. The conductor crimping portion includes serrations that are formed at least a part of the inner surface thereof and retains the conductor of the electric cable inside the conductor crimping portion and at least one bead that protrudes from the inner surface.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Yazaki Corporation
    Inventors: Takaya KONDOU, Masanori ONUMA, Yoshitaka ITO
  • Patent number: 8353732
    Abstract: A connector in which terminal extraction work using an extraction jig can surely be done when necessary and also at the normal time, a terminal of the other connector can be connected to a terminal of the inside of a terminal receiving chamber without any mistakes and fear of a poor fit can be removed is provided. In the connector having two connector housings 20, 10 attached with the connector housings stacked mutually, a connector front wall 17 with which the front ends of terminal receiving chambers 21 of the first connector housing 20 are covered is formed integrally to the second connector housing 10, and a terminal insertion opening 18 opened in the connector front wall 17 is provided so as to deviate from the front of a first terminal 70 and be positioned in the front of a first lance 22 for locking the first terminal when both the connector housings are held in a temporary locking position.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: January 15, 2013
    Assignee: Yazaki Corporation
    Inventor: Yoshitaka Ito
  • Publication number: 20120295491
    Abstract: A connector housing includes an upper housing having a front end wall that defines the front end of a terminal containing chamber, and a lower housing having an opening section due to the lack of a front end wall. The front end wall of the upper housing has an insertion hole. The lower housing has the terminal containing chamber, and is disposed with a lance which is formed by using the opening section on the front end of the lower housing as a through hole. The upper housing and the lower housing have restricting portions which inhibit the relative displacement of both housings in the front and back direction when united, and a locking mechanism for maintaining the united state by restricting the upper housing and lower housing from separating in the upper or lower direction.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 22, 2012
    Applicant: YAZAKI CORPORATION
    Inventor: Yoshitaka ITO
  • Patent number: 8187041
    Abstract: In a coupling connector formed by stacking two connector housings (10A, 20A) vertically on each other and coupling the two connector housings (10A, 20A) to each other, the two connector housings (10A, 20A) having terminal housing chambers (11, 21) into which terminals (111, 121) are inserted from rear ends thereof insertion recessed portions (16, 25) are provided on upper and lower surfaces of the stacked connector housings, respectively, while shifting positions thereof from each other, and terminal engaging projection portions (15, 26) are provided, which are inserted into the insertion recessed portions of the opposite-side connector housings opposite thereto when the connector housings are stacked on each other, and thereby inhibit rearward detachment of the terminals inserted into the terminal housing chambers of the opposite-side connector housings.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: May 29, 2012
    Assignee: Yazaki Corporation
    Inventor: Yoshitaka Ito
  • Publication number: 20120023281
    Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
    Type: Application
    Filed: March 24, 2011
    Publication date: January 26, 2012
    Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
  • Publication number: 20120021633
    Abstract: A connector in which terminal extraction work using an extraction jig can surely be done when necessary and also at the normal time, a terminal of the other connector can be connected to a terminal of the inside of a terminal receiving chamber without any mistakes and fear of a poor fit can be removed is provided. In the connector having two connector housings 20, 10 attached with the connector housings stacked mutually, a connector front wall 17 with which the front ends of terminal receiving chambers 21 of the first connector housing 20 are covered is formed integrally to the second connector housing 10, and a terminal insertion opening 18 opened in the connector front wall 17 is provided so as to deviate from the front of a first terminal 70 and be positioned in the front of a first lance 22 for locking the first terminal when both the connector housings are held in a temporary locking position.
    Type: Application
    Filed: January 20, 2010
    Publication date: January 26, 2012
    Applicant: YAZAKI CORPORATION
    Inventor: Yoshitaka Ito
  • Publication number: 20110246707
    Abstract: A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition.
    Type: Application
    Filed: March 13, 2011
    Publication date: October 6, 2011
    Inventor: Yoshitaka Ito