Patents by Inventor Yoshitaka Narita

Yoshitaka Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190112668
    Abstract: The present invention provides a kit or device for the detection of malignant brain tumor, and a method for detecting malignant brain tumor. The present invention relates to a kit or device for the detection of malignant brain tumor, comprising nucleic acid(s) capable of specifically binding to predetermined miRNA(s) in a sample of a subject, and a method for detecting malignant brain tumor, comprising measuring the miRNA(s) in vitro.
    Type: Application
    Filed: March 31, 2017
    Publication date: April 18, 2019
    Applicants: TORAY INDUSTRIES, INC., NATIONAL CANCER CENTER
    Inventors: Makiko YOSHIMOTO, Satoko KOZONO, Junpei KAWAUCHI, Satoshi KONDOU, Hitoshi NOBUMASA, Takahiro OCHIYA, Yoshitaka NARITA, Makoto OHNO
  • Patent number: 9839169
    Abstract: A printed board transport apparatus includes a first conveyor which transports a printed board between a working portion and printed board loading/unloading portions of a working apparatus, and a second conveyor installed in the printed board loading/unloading portions. The first conveyor has a function of rotating a first transport member, and a function of moving in a direction parallel to the transport direction. The second conveyor transports the printed board by rotating a second transport member. After the length of a downstream portion of the printed board, which is placed on a conveyor on the downstream side, has reached a support length, the first conveyor moves toward the working portion by changing the rotational speed of the first transport member to a rotational speed for conveyor movement.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: December 5, 2017
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventor: Yoshitaka Narita
  • Patent number: 9609795
    Abstract: Provided is a solder supply method of supplying, onto a mask sheet, solder to be printed on a printed circuit board. The method includes calculating an amount of solder supplied for a plurality of points in an X direction that is a lengthwise direction of a squeegee, and changing the amount of solder supplied at each point in the X direction based on a result of the calculation.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 28, 2017
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yoshitaka Narita, Takeshi Fujimoto, Hidetoshi Sato
  • Publication number: 20170034966
    Abstract: A printed board transport apparatus includes a first conveyor which transports a printed board between a working portion and printed board loading/unloading portions of a working apparatus, and a second conveyor installed in the printed board loading/unloading portions. The first conveyor has a function of rotating a first transport member, and a function of moving in a direction parallel to the transport direction. The second conveyor transports the printed board by rotating a second transport member. After the length of a downstream portion of the printed board, which is placed on a conveyor on the downstream side, has reached a support length, the first conveyor moves toward the working portion by changing the rotational speed of the first transport member to a rotational speed for conveyor movement.
    Type: Application
    Filed: April 7, 2014
    Publication date: February 2, 2017
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventor: Yoshitaka NARITA
  • Patent number: 9468135
    Abstract: A substrate conveying system includes a mounting device conveyor for conveying a printed substrate in a first horizontal direction, an upstream-side conveyor, a downstream-side conveyor, and a buffer conveyor. The mounting device conveyor has a function of moving the printed substrate in a horizontal Y direction perpendicular to the conveying direction. The upstream-side conveyor is spaced apart from the downstream-side conveyor in the Y direction. The buffer conveyor has a function of conveying the printed substrate in the first direction, and a function of moving the printed substrate in the Y direction. When the mounting device conveyor and the buffer conveyor are positioned in the same position in the Y direction, the printed substrate is transferred from one of these conveyors to the other.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 11, 2016
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yoshitaka Narita, Kazuaki Yamada
  • Publication number: 20150382519
    Abstract: A substrate conveying system includes a mounting device conveyor for conveying a printed substrate in a first horizontal direction, an upstream-side conveyor , a downstream-side conveyor , and a buffer conveyor. The mounting device conveyor has a function of moving the printed substrate in a horizontal Y direction perpendicular to the conveying direction. The upstream-side conveyor is spaced apart from the downstream-side conveyor in the Y direction. The buffer conveyor has a function of conveying the printed substrate in the first direction, and a function of moving the printed substrate in the Y direction. When the mounting device conveyor and the buffer conveyor are positioned in the same position in the Y direction, the printed substrate is transferred from one of these conveyors to the other.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 31, 2015
    Inventors: Yoshitaka NARITA, Kazuaki YAMADA
  • Publication number: 20140115874
    Abstract: Provided is a solder supply method of supplying, onto a mask sheet, solder to be printed on a printed circuit board. The method includes calculating an amount of solder supplied for a plurality of points in an X direction that is a lengthwise direction of a squeegee, and changing the amount of solder supplied at each point in the X direction based on a result of the calculation.
    Type: Application
    Filed: August 8, 2013
    Publication date: May 1, 2014
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yoshitaka NARITA, Takeshi FUJIMOTO, Hidetoshi SATO
  • Patent number: 7285764
    Abstract: An imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well storing the charges; a modulation transistor having a channel threshold voltage controlled by the stored charges and outputting a corresponding signal; a transfer control element having a control end coupled to a control end of the modulation transistor and controlling the potential barrier of a transfer channel between the accumulation and modulation wells, and controlling transfer of the charges; an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging charges overflowing from the accumulation well during a period except for the charges transfer period; and a residual charge discharging control element controlling the potential barrier of a residual electric charge discharging channel coupled to the modulation we
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: October 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Patent number: 6946638
    Abstract: A solid-state imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well holding the charges from the accumulation well; a modulation transistor controlled by the charges held in the modulation well and that outputs a signal corresponding to the charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation and modulation wells to control transfer of the charges; an unwanted charges discharging control element controlling the potential barrier of an unwanted charges discharging channel coupled to the accumulation well, and discharging charges that overflow from the accumulation well during a period other than the transfer period when the photo-generated charges are transferred; and a residual charges discharging control element controlling the potential barrier of a residual charges discharging channel coupled to the modulation well, and discharging residua
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: September 20, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Publication number: 20050087781
    Abstract: An imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well storing the charges; a modulation transistor having a channel threshold voltage controlled by the stored charges and outputting a corresponding signal; a transfer control element having a control end coupled to a control end of the modulation transistor and controlling the potential barrier of a transfer channel between the accumulation and modulation wells, and controlling transfer of the charges; an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging charges overflowing from the accumulation well during a period except for the charges transfer period; and a residual charge discharging control element controlling the potential barrier of a residual electric charge discharging channel coupled to the modulation we
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Publication number: 20050087672
    Abstract: A solid-state imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well holding the charges from the accumulation well; a modulation transistor controlled by the charges held in the modulation well and that outputs a signal corresponding to the charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation and modulation wells to control transfer of the charges; an unwanted charges discharging control element controlling the potential barrier of an unwanted charges discharging channel coupled to the accumulation well, and discharging charges that overflow from the accumulation well during a period other than the transfer period when the photo-generated charges are transferred; and a residual charges discharging control element controlling the potential barrier of a residual charges discharging channel coupled to the modulation well, and discharging residua
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Patent number: 5917247
    Abstract: The semiconductor memory device disclosed includes an element isolation insulating film, a first diffusion layer, a second diffusion layer. The first diffusion layer of a first conductivity type is buried inside the semiconductor substrate, and has an impurity concentration higher than that of the semiconductor substrate. The first diffusion layer is provided at a shallow position in the area where the element isolation insulating film is formed and is provided a deep position in the area where the element isolation insulating film is not formed. The second diffusion layer of a second conductivity type is at an area ranging from the surface of the semiconductor substrate to the first diffusion layer inside the semiconductor substrate. A p-n junction is formed at a junction portion between the first and second diffusion layers. The structure thus configured has a high resistance to soft errors.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 29, 1999
    Assignee: NEC Corporation
    Inventor: Yoshitaka Narita
  • Patent number: 5410161
    Abstract: Dummy transistors (each composed of a dummy gate electrode and n.sup.+ -diffused layers) are disposed adjacent to a transistor for characteristic checking which is composed of a gate electrode, n.sup.+ -diffused layers and aluminum interconnection layers. They are arranged in the same density as that of regular transistors in a product. This decreases a difference in size between the characteristic checking transistor and that in the regular transistors in the product so that the former can be truly representative of the latter.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: April 25, 1995
    Assignee: NEC Corporation
    Inventor: Yoshitaka Narita