Patents by Inventor Yoshito Akutagawa
Yoshito Akutagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11764138Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.Type: GrantFiled: July 24, 2020Date of Patent: September 19, 2023Assignee: TOPPAN PRINTING CO., LTD.Inventors: Osamu Koga, Yasuyuki Hitsuoka, Yoshito Akutagawa
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Publication number: 20200357734Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: TOPPAN PRINTING CO.,LTD.Inventors: Osamu KOGA, Yasuyuki HITSUOKA, Yoshito AKUTAGAWA
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Patent number: 9735099Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.Type: GrantFiled: December 20, 2016Date of Patent: August 15, 2017Assignee: TOPPAN PRINTING CO., LTD.Inventors: Akane Kobayashi, Yoshito Akutagawa
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Publication number: 20170103945Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Applicant: TOPPAN PRINTING CO., LTD.Inventors: Akane KOBAYASHI, Yoshito AKUTAGAWA
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Patent number: 8411197Abstract: An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.Type: GrantFiled: October 20, 2004Date of Patent: April 2, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi
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Patent number: 8302843Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.Type: GrantFiled: March 27, 2009Date of Patent: November 6, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Matsui, Yutaka Makino, Yoshito Akutagawa
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Publication number: 20120251968Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroyuki MATSUI, Yutaka Makino, Yoshito Akutagawa
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Patent number: 8216934Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: GrantFiled: December 22, 2010Date of Patent: July 10, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
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Publication number: 20120129335Abstract: A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.Type: ApplicationFiled: July 28, 2011Publication date: May 24, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masamitsu IKUMO, Hiroyuki Yoda, Yoshito Akutagawa
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Publication number: 20110092065Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Eiji YOSHIDA, Takao OHNO, Yoshito AKUTAGAWA, Koji SAWAHATA, Masataka MIZUKOSHI, Takao NISHIMURA, Akira TAKASHIMA, Mitsuhisa WATANABE
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Patent number: 7923303Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.Type: GrantFiled: November 11, 2009Date of Patent: April 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
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Patent number: 7888258Abstract: A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere.Type: GrantFiled: June 23, 2008Date of Patent: February 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Yoshito Akutagawa, Hiroyuki Matsui, Yutaka Makino
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Patent number: 7884459Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: GrantFiled: September 15, 2008Date of Patent: February 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
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Publication number: 20100052212Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.Type: ApplicationFiled: November 11, 2009Publication date: March 4, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yoshito AKUTAGAWA, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
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Patent number: 7638367Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.Type: GrantFiled: July 11, 2006Date of Patent: December 29, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
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Patent number: 7616250Abstract: An image capturing device is disclosed that includes a light receiving element having a light receiving surface, a plate-like transparent member provided on the light receiving surface of the light receiving element, and resin provided to at least the periphery of the plate-like transparent member. The plate-like transparent member includes a first principal plane positioned on the light receiving element side and a second principal plane opposite the first principal plane. The first principal plane is greater in area than the second principal plane.Type: GrantFiled: November 23, 2004Date of Patent: November 10, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi
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Publication number: 20090184156Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.Type: ApplicationFiled: March 27, 2009Publication date: July 23, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki Matsui, Yutaka Makino, Yoshito Akutagawa
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Publication number: 20090087984Abstract: A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere.Type: ApplicationFiled: June 23, 2008Publication date: April 2, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yoshito AKUTAGAWA, Hiroyuki MATSUI, Yutaka MAKINO
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Publication number: 20090008798Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: ApplicationFiled: September 15, 2008Publication date: January 8, 2009Applicant: FUJITSU LIMITEDInventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
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Publication number: 20070196957Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.Type: ApplicationFiled: July 11, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka