Patents by Inventor Yoshito Akutagawa

Yoshito Akutagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357734
    Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: TOPPAN PRINTING CO.,LTD.
    Inventors: Osamu KOGA, Yasuyuki HITSUOKA, Yoshito AKUTAGAWA
  • Patent number: 9735099
    Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: August 15, 2017
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Akane Kobayashi, Yoshito Akutagawa
  • Publication number: 20170103945
    Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Akane KOBAYASHI, Yoshito AKUTAGAWA
  • Patent number: 8411197
    Abstract: An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi
  • Patent number: 8302843
    Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Matsui, Yutaka Makino, Yoshito Akutagawa
  • Publication number: 20120251968
    Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.
    Type: Application
    Filed: June 14, 2012
    Publication date: October 4, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroyuki MATSUI, Yutaka Makino, Yoshito Akutagawa
  • Patent number: 8216934
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20120129335
    Abstract: A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.
    Type: Application
    Filed: July 28, 2011
    Publication date: May 24, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masamitsu IKUMO, Hiroyuki Yoda, Yoshito Akutagawa
  • Publication number: 20110092065
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Eiji YOSHIDA, Takao OHNO, Yoshito AKUTAGAWA, Koji SAWAHATA, Masataka MIZUKOSHI, Takao NISHIMURA, Akira TAKASHIMA, Mitsuhisa WATANABE
  • Patent number: 7923303
    Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: April 12, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
  • Patent number: 7888258
    Abstract: A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 15, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshito Akutagawa, Hiroyuki Matsui, Yutaka Makino
  • Patent number: 7884459
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20100052212
    Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.
    Type: Application
    Filed: November 11, 2009
    Publication date: March 4, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Yoshito AKUTAGAWA, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
  • Patent number: 7638367
    Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
  • Patent number: 7616250
    Abstract: An image capturing device is disclosed that includes a light receiving element having a light receiving surface, a plate-like transparent member provided on the light receiving surface of the light receiving element, and resin provided to at least the periphery of the plate-like transparent member. The plate-like transparent member includes a first principal plane positioned on the light receiving element side and a second principal plane opposite the first principal plane. The first principal plane is greater in area than the second principal plane.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: November 10, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi
  • Publication number: 20090184156
    Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 23, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroyuki Matsui, Yutaka Makino, Yoshito Akutagawa
  • Publication number: 20090087984
    Abstract: A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere.
    Type: Application
    Filed: June 23, 2008
    Publication date: April 2, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Yoshito AKUTAGAWA, Hiroyuki MATSUI, Yutaka MAKINO
  • Publication number: 20090008798
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: September 15, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20070196957
    Abstract: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus.
    Type: Application
    Filed: July 11, 2006
    Publication date: August 23, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yoshito Akutagawa, Izumi Kobayashi, Naoyuki Watanabe, Susumu Moriya, Toshiyuki Honda, Noboru Hayasaka
  • Publication number: 20060023108
    Abstract: An image capturing device is disclosed that includes a light receiving element having a light receiving surface, a plate-like transparent member provided on the light receiving surface of the light receiving element, and resin provided to at least the periphery of the plate-like transparent member. The plate-like transparent member includes a first principal plane positioned on the light receiving element side and a second principal plane opposite the first principal plane. The first principal plane is greater in area than the second principal plane.
    Type: Application
    Filed: November 23, 2004
    Publication date: February 2, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi