Patents by Inventor Yoshitsugu Funada

Yoshitsugu Funada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6311888
    Abstract: This invention provides a resin film preferably used for mounting a semiconductor chip on a substrate through flip-chip connection, and a method based on the use of such a resin film. The resin film has a laminated B/A/B structure where a first resin layer (A) having inorganic particles dispersed in an insulating resin is sandwiched by second and third resin layers (B) having no inorganic particles in their insulating resins.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Rieka Ohuchi
  • Publication number: 20010011111
    Abstract: A resin matrix with resistances to alkali and acid includes at least any one of insulative organic particles and insulative composite particles having an organic component and an inorganic component with the total amount of these particles being in the range of 5-50% by volume, wherein the insulative organic particles and the organic component of the insulative composite particles are allowed to be corroded by either alkali or acid, and wherein not less than 90% by volume of the insulative organic particles and insulative component particles have a particle diameter in the range of 1-20 micrometers.
    Type: Application
    Filed: March 23, 2001
    Publication date: August 2, 2001
    Applicant: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui
  • Patent number: 6232398
    Abstract: A resin matrix with resistances to alkali and acid such as a fluorene-containing epoxy acrylate and/or a benzocyclobutene resin includes at least any one of insulative organic particles and insulative composite particles having an organic component and an inorganic component with the total amount of these particles being in the range of 5-50% by volume, wherein the insulative organic particles and the organic component of the insulative composite particles are allowed to be corroded by either alkali or acid, and wherein not less than 90% by volume of the insulative organic particles and insulative composite particles have a particle diameter in the range of 1-20 micrometers.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: May 15, 2001
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui
  • Patent number: 6214446
    Abstract: This invention provides a resin film preferably used for mounting a semiconductor chip on a substrate through flip-chip connection, and a method based on the use of such a resin film. The resin film has a laminated B/A/B structure where a first resin layer (A) having inorganic particles dispersed in an insulating resin is sandwiched by second and third resin layers (B) having no inorganic particles in their insulating resins.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 10, 2001
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Rieka Ohuchi
  • Patent number: 6078229
    Abstract: It is an object on the invention to provide a SAW device sealed by resin, which is low priced and suited for decreasing its thickness and weight and requires no particular course for processing a substrate, and a method for fabricating the same. A functional surface of a piezoelectric substrate provided with interdigtal transducers and a mounting surface of a circuit substrate are opposed to each other to form vibration cavities for surface wave propagation areas therebetween. Electrical power is supplied to the piezoelectric substrate from the circuit substrate via electrode pads formed on respective inner surface of both the substrate and bumps inserted therebetween. A resin film adheres to the respective inner surfaces of both the substrates except the surface wave propagation areas to shield the vibration cavity from the environmental space. Apertures are previously formed at predetermined parts of the resin film by means of a laser.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Michinobu Tanioka
  • Patent number: 5972739
    Abstract: A resin-encapsulated semiconductor device includes a semiconductor chip consisting of a semiconductor element having metal bumps and metal leads electrically connected to the metal bumps and having a surface-treated layer obtained by a surface treatment, and a resin film stacked on the outer side of the semiconductor chip and tightly adhered to the semiconductor chip by a heat treatment and pressurization treatment.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui
  • Patent number: 5830563
    Abstract: This invention relates to an interconnection structure comprising one or more insulating films and one or more layers of conductor electrode patterns, wherein at least one of the insulating films consists of a fluorene skeleton-containing epoxy acrylate resin, and to a method of making a multilayer interconnection structure including the steps of roughening the surface of an insulating resin layer and forming a conductor thereon by electroless plating, wherein the average roughness (Ra), maximum roughness (Ry) and conductor thickness (T) of the roughened surface of the insulating resin layer satisfy the following relations:0.2.ltoreq.Ra.ltoreq.0.6 (unit: .mu.m) (1)0.02.ltoreq.Ra/T.ltoreq.0.2 (2)0.05.ltoreq.Ry/T.ltoreq.0.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: November 3, 1998
    Assignee: NEC Corporation
    Inventors: Tadanori Shimoto, Yoshitsugu Funada, Koji Matsui, Yuzo Shimada, Kazuaki Utsumi
  • Patent number: 5681648
    Abstract: The present invention provides a novel printed wiring board which has an insulating substrate. The printed wiring board also has a metal compound layer formed on a surface of the insulating substrate, wherein the metal compound layer is made of a metal compound having a sufficient insulating property and showing a reduction to a metal. The metal compound layer has a surface formed thereon with a metal wiring pattern which is formed by selective reduction of the above metal compound of the metal compound layer. The printed wiring board also has a palladium-displacement plating layer formed on the metal wiring pattern. The printed wiring board also has an electroless plating layer.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: October 28, 1997
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui
  • Patent number: 5372872
    Abstract: A multilayer printed circuit board reducing cross-talk noise between signal interconnection layers and between through-holes for connecting the signal interconnection layers is disclosed. The multilayer printed circuit board has printed substrates each formed thereon an interconnection layer, and prepreg sandwiched therebetween. The prepreg comprises an reinforcement lattice cloth formed of rovings of a electroconductive material maintained at a ground potential and a dielectric resin impregnated thereinto and forming a dielectric solid layer having through-holes penetrating therethrough. The electroconductive reinforcement lattice cloth functions as a ground layer between signal interconnection layers and between through-holes . The rovings may be of a metal or a semiconductive material such as carbon fiber. The multilayer printed circuit board is superior in heat resistance, dimensional stability and mechanical strength.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui