Patents by Inventor Yoshitsugu Yamamoto
Yoshitsugu Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854523Abstract: A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.Type: GrantFiled: October 24, 2016Date of Patent: December 1, 2020Assignee: Mitsubishi Electric CorporationInventors: Koichiro Nishizawa, Yoshitsugu Yamamoto, Katsumi Miyawaki, Shinsuke Watanabe, Toshihiko Shiga
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Publication number: 20200185285Abstract: A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.Type: ApplicationFiled: October 24, 2016Publication date: June 11, 2020Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Yoshitsugu YAMAMOTO, Katsumi MIYAWAKI, Shinsuke WATANABE, Toshihiko SHIGA
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Publication number: 20170294887Abstract: A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.Type: ApplicationFiled: November 25, 2016Publication date: October 12, 2017Applicant: Mitsubishi Electric CorporationInventors: Yoshitaka KAMO, Yoshitsugu YAMAMOTO
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Patent number: 9508564Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.Type: GrantFiled: July 19, 2013Date of Patent: November 29, 2016Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Yokoyama, Kazuyo Endo, Jun Fujita, Shinnosuke Soda, Kazuyasu Nishikawa, Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue
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Patent number: 9159654Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.Type: GrantFiled: October 2, 2014Date of Patent: October 13, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
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Publication number: 20150243530Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.Type: ApplicationFiled: July 19, 2013Publication date: August 27, 2015Applicant: Mitsubishi Electric CorporationInventors: Yoshinori Yokoyama, Kazuyo Endo, Jun Fujita, Shinnosuke Soda, Kazuyasu Nishikawa, Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue
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Patent number: 9117742Abstract: A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.Type: GrantFiled: February 7, 2014Date of Patent: August 25, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroyuki Kinoshita, Yoshitsugu Yamamoto, Tetsuo Kunii
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Publication number: 20150054137Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.Type: ApplicationFiled: October 2, 2014Publication date: February 26, 2015Inventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
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Patent number: 8912099Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: GrantFiled: July 30, 2013Date of Patent: December 16, 2014Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Publication number: 20140353674Abstract: A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.Type: ApplicationFiled: February 7, 2014Publication date: December 4, 2014Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki Kinoshita, Yoshitsugu Yamamoto, Tetsuo Kunii
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Patent number: 8878333Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.Type: GrantFiled: July 10, 2012Date of Patent: November 4, 2014Assignee: Mitsubishi Electric CorporationInventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
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Patent number: 8816493Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.Type: GrantFiled: June 19, 2013Date of Patent: August 26, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
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Publication number: 20140175615Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film.Type: ApplicationFiled: September 25, 2013Publication date: June 26, 2014Applicant: Mitsubishi Electric CorporationInventors: Yoichi Nogami, Yoshitsugu Yamamoto, Yoshinori Yokoyama, Shinnosuke Soda
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Publication number: 20140134835Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.Type: ApplicationFiled: July 30, 2013Publication date: May 15, 2014Applicant: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
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Publication number: 20140077280Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.Type: ApplicationFiled: June 19, 2013Publication date: March 20, 2014Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
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Publication number: 20130056875Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.Type: ApplicationFiled: July 10, 2012Publication date: March 7, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Youichi NOGAMI, Hidetoshi KOYAMA, Yoshitsugu YAMAMOTO
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Patent number: 8247844Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.Type: GrantFiled: October 7, 2009Date of Patent: August 21, 2012Assignee: Mitsubishi Electric CorporationInventors: Toshiyuki Oishi, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
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Patent number: 8232609Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.Type: GrantFiled: July 1, 2010Date of Patent: July 31, 2012Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
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Publication number: 20110006351Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.Type: ApplicationFiled: July 1, 2010Publication date: January 13, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
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Publication number: 20100244041Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.Type: ApplicationFiled: October 7, 2009Publication date: September 30, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshiyuki OISHI, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue