Patents by Inventor Yoshitsugu Yamamoto

Yoshitsugu Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10320284
    Abstract: An inverter device uses an inverter to convert DC voltage supplied from a rectifying component to AC voltage and applies the AC voltage to an inductive load. The inverter device includes a shunt resistor provided on a direct-current link interconnecting the rectifying component and the inverter, a first terminal passing current to the shunt resistor, a second terminal to which the current from the shunt resistor flows, and a printed board having a conductive pattern with first and second conductive pattern components joining the shunt resistor and the first and second terminals, respectively. The first conductive pattern component includes a first central region connecting right and left side ends of the shunt resistor to right and left side ends of the first terminal, and first right and left side protruding regions. A ratio of areas of the first left and right side protruding regions is 0.6 to 1.6.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 11, 2019
    Assignee: Daikin Industries, Ltd.
    Inventors: Hirotaka Doi, Hiroshi Doumae, Takuji Koyama, Michiya Takezoe, Keito Kotera, Masahiro Yamamoto, Yoshitsugu Koyama, Sumio Kagimura
  • Publication number: 20170294887
    Abstract: A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.
    Type: Application
    Filed: November 25, 2016
    Publication date: October 12, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshitaka KAMO, Yoshitsugu YAMAMOTO
  • Patent number: 9508564
    Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Yokoyama, Kazuyo Endo, Jun Fujita, Shinnosuke Soda, Kazuyasu Nishikawa, Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue
  • Patent number: 9159654
    Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 13, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
  • Publication number: 20150243530
    Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 27, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori Yokoyama, Kazuyo Endo, Jun Fujita, Shinnosuke Soda, Kazuyasu Nishikawa, Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue
  • Patent number: 9117742
    Abstract: A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 25, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Kinoshita, Yoshitsugu Yamamoto, Tetsuo Kunii
  • Publication number: 20150054137
    Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
  • Patent number: 8912099
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
  • Publication number: 20140353674
    Abstract: A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.
    Type: Application
    Filed: February 7, 2014
    Publication date: December 4, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kinoshita, Yoshitsugu Yamamoto, Tetsuo Kunii
  • Patent number: 8878333
    Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
  • Patent number: 8816493
    Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 26, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
  • Publication number: 20140175615
    Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film.
    Type: Application
    Filed: September 25, 2013
    Publication date: June 26, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Yoshinori Yokoyama, Shinnosuke Soda
  • Publication number: 20140134835
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Application
    Filed: July 30, 2013
    Publication date: May 15, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
  • Publication number: 20140077280
    Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.
    Type: Application
    Filed: June 19, 2013
    Publication date: March 20, 2014
    Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
  • Publication number: 20130056875
    Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.
    Type: Application
    Filed: July 10, 2012
    Publication date: March 7, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Youichi NOGAMI, Hidetoshi KOYAMA, Yoshitsugu YAMAMOTO
  • Patent number: 8247844
    Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: August 21, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshiyuki Oishi, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
  • Patent number: 8232609
    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
  • Publication number: 20110006351
    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 13, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
  • Publication number: 20100244041
    Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.
    Type: Application
    Filed: October 7, 2009
    Publication date: September 30, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Toshiyuki OISHI, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
  • Patent number: 7700972
    Abstract: A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor substrate and exposes a part of a lower surface of the AlN layer, in a location facing the first opening. A upper electrode is exposed on an upper surface of the AlN layer in the first opening; and a lower electrode is disposed on a lower surface of the AlN layer in the second opening.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: April 20, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Takeuchi, Yoshitsugu Yamamoto