Abstract: A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.

Abstract: A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.

Abstract: A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.

Abstract: A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.

Abstract: A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.

Abstract: A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract: A data transfer control device includes an ATA device-side I/F which transfers data between the data transfer control device and an ATA host through a bus ATABUS1, an ATA host-side I/F which transfers data between the data transfer control device and an ATA device through a bus ATABUS2, a first interface which transfers data through a first bus, and a transfer controller which controls data transfer among the device-side I/F, the host-side I/F, and the first interface.

Abstract: A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.

Abstract: A data transfer control device includes an OTG (state) controller which controls a plurality of states including a host operation state and a peripheral operation state, a host controller which is connected with a transceiver during the host operation, a peripheral controller which is connected with the transceiver during the peripheral operation, a register section including transfer condition registers which are used commonly during the host operation and the peripheral operation, and a buffer controller which controls access to a packet buffer used commonly by the host controller and the peripheral controller. Pipe regions PIPE0 to PIPEe are allocated in the packet buffer during the host operation, and endpoint regions EP0 to EPe are allocated in the packet buffer during the peripheral operation.

Abstract: An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label tl of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within tl, when the response packet is received.

Abstract: An electronic instrument including: an upstream port UPPT provided on a side surface SF1 of the electronic instrument; a downstream port DWPT provided on a side surface SF2 which is a surface of the electronic instrument and opposite to the side surface SF1; and a data transfer control device which is connected to the upstream port UPPT and the downstream port DWPT and controls data transfer through the upstream port UPPT and data transfer through the downstream port DWPT.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been received in response to an IN token issued to the first USB device, the transfer controller issues an OUT token to the second USB device and transmits the received data from the first USB device to the second USB device. The transfer controller issues an IN token to at least one of the USB devices which has declared itself to be a local area network (LAN) node.

Abstract: A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract: A data transfer control device including a buffer is provided which includes an EP2 area (a data storage area set to FIFO) and a CSW area (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2. When a phase has switched from a USE data phase (data transport) to a status phase (status transport), the information read area is switched from the EP2 area to the CSW area. and IN data to be transferred from the end point EP2 to a host is read from the CSW area. A CSW0 area for success status and a CSW1 area for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.

Abstract: A data transfer control device includes an ATA device-side I/F which transfers data between the data transfer control device and an ATA host through a bus ATABUS1, an ATA host-side I/F which transfers data between the data transfer control device and an ATA device through a bus ATABUS2, a first interface which transfers data through a first bus, and a transfer controller which controls data transfer among the device-side I/F, the host-side I/F, and the first interface.

Abstract: A buffer is provided with a CBW area (a randomly accessible command storage area) and an EP1 area (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP1. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EP1 area and OUT data transferred from the host to the end point EP1 is written into the EP1 area. The area switches from the CBW area to the EP1 area on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.

Abstract: The objective is to provide a data transfer control device and electronic equipment that make it possible to switch the frequency of a generated clock dynamically, without causing any operating errors. The data transfer control device includes a clock generation circuit which generates clocks CLKH and CLKF and a clock control circuit which generates a system clock SYCLK based on CLKH and CLKF. The autonomous operation of a PLL60M that generates CLKF is enabled before the autonomous operation of a PLL480M that generates CLKH is disabled, and the generation source of SYCLK is switched from CLKH to CLKF after the autonomous operation of the PLL60M has stabilized. On condition that CLKH becomes “0”, SYCLK is set to “0” for a given period only; and on condition that CLKF becomes “0”, SYCLK is generated based on CLKF. When the mode switches from HS mode FS mode under USB 2.0, the operation of the PLL480M is disabled, reducing the power consumption.