Patents by Inventor Yoshiyuki Kawakami
Yoshiyuki Kawakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10232601Abstract: A decoration method of a printed matter includes: forming a printed layer on a surface of a sheet or of a mounting paper with a transparent varnish, printing a predetermined pattern on the surface of the printed layer by an ink or by a resin which are capable of being adhered to the printed layer; and pressing a metal foil onto the pattern printed by the ink or the resin with an adhesive agent. The adhesive agent does not adhere to the printed layer but adheres to the pattern. As a result, the metal foil 6 is printed only to the pattern.Type: GrantFiled: March 10, 2017Date of Patent: March 19, 2019Assignee: Japan Card Products Co., Ltd.Inventors: Yoshiyuki Kawakami, Tomoki Tsunoda
-
Publication number: 20170259551Abstract: A decoration method of a printed matter includes: forming a printed layer on a surface of a sheet or of a mounting paper with a transparent varnish, printing a predetermined pattern on the surface of the printed layer by an ink or by a resin which are capable of being adhered to the printed layer; and pressing a metal foil onto the pattern printed by the ink or the resin with an adhesive agent. The adhesive agent does not adhere to the printed layer but adheres to the pattern. As a result, the metal foil 6 is printed only to the pattern.Type: ApplicationFiled: March 10, 2017Publication date: September 14, 2017Inventors: Yoshiyuki KAWAKAMI, Tomoki TSUNODA
-
Publication number: 20130196987Abstract: The present invention provides compounds, methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis.Type: ApplicationFiled: October 30, 2012Publication date: August 1, 2013Applicant: EISAI CO., LTD.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 8329742Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.Type: GrantFiled: July 20, 2010Date of Patent: December 11, 2012Assignee: EISAI Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
-
Publication number: 20110144101Abstract: The present invention provides methods for the use of compounds having formula (I) in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, t, X, Y, Z, and n are as defined herein.Type: ApplicationFiled: July 20, 2010Publication date: June 16, 2011Applicant: EISAI CO., LTD.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 7915306Abstract: The present invention provides compositions comprising compounds having formula (I): and additionally provides methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein. In certain embodiments, the compositions are for systemic (e.g., oral) administration. In certain embodiments, methods for the treatment of various disorders including inflammatory or autoimmune disorders comprise systemically (e.g., orally) administering to a subject in need thereof a therapeutically effective amount of a compound of formula (I).Type: GrantFiled: September 9, 2003Date of Patent: March 29, 2011Assignee: Eisai Co., Ltd.Inventors: Kenichi Chiba, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Ray Wood, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 7799827Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.Type: GrantFiled: March 7, 2003Date of Patent: September 21, 2010Assignee: Eisai Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-André Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 7541625Abstract: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.Type: GrantFiled: March 3, 2006Date of Patent: June 2, 2009Assignee: Panasonic CorporationInventor: Yoshiyuki Kawakami
-
Publication number: 20080164496Abstract: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.Type: ApplicationFiled: March 3, 2006Publication date: July 10, 2008Inventor: Yoshiyuki Kawakami
-
Publication number: 20070143723Abstract: In timing verification considering process variations in the fabrication of semiconductor integrated circuits, parasitic element extraction results are obtained with high accuracy by considering variations in interconnect configuration occurring randomly inside LSI to perform timing verification of worst-case or best-case simulation. For example, a plurality of capacitance libraries are prepared according to process variations in the fabrication of semiconductor integrated circuits, such as variations in interconnect width, interconnect film thickness and interlayer film thickness, and one is selected among these capacitance libraries properly according to the target layout. In this way, parasitic element extraction results for worst-case or best-case simulation can be obtained with high accuracy for the target layout.Type: ApplicationFiled: December 21, 2006Publication date: June 21, 2007Inventor: Yoshiyuki Kawakami
-
Publication number: 20060247448Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.Type: ApplicationFiled: March 7, 2003Publication date: November 2, 2006Applicant: Eisai Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmanage, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John Wang, Satoshi Yamamoto, Naoki Yoneda
-
Publication number: 20040224936Abstract: The present invention provides compositions comprising compounds having formula (I): 1Type: ApplicationFiled: September 9, 2003Publication date: November 11, 2004Inventors: Kenichi Chiba, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmange, Atsushi Inoue, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John (Yuan) Wang, Ray Wood, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 6795802Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.Type: GrantFiled: March 19, 2001Date of Patent: September 21, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
-
Patent number: 6498515Abstract: A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degType: GrantFiled: May 13, 2002Date of Patent: December 24, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Kawakami, Nobufusa Iwanishi
-
Publication number: 20020140460Abstract: A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degType: ApplicationFiled: May 13, 2002Publication date: October 3, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Kawakami, Nobufusa Iwanishi
-
Patent number: 6396307Abstract: A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degType: GrantFiled: May 19, 2000Date of Patent: May 28, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Kawakami, Nobufusa Iwanishi
-
Publication number: 20020022949Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.Type: ApplicationFiled: March 19, 2001Publication date: February 21, 2002Inventors: Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
-
Patent number: 6278964Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.Type: GrantFiled: May 29, 1998Date of Patent: August 21, 2001Assignees: Matsushita Electric Industrial Co., Ltd., BTA Technology Inc.Inventors: Jingkun Fang, Hirokazu Yonezawa, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
-
Patent number: 6047247Abstract: There is provided a hot-carrier-delay-degradation estimation method of estimating, based on the actual operation of an LSI, deterioration in reliability thereof due to the influence of hot carriers. At a delay calculation step, there are calculated, for the cells of an LSI serving as the object of timing verification, delays, input slew and output load capacitances based on circuit information and a delay library containing delay parameters. At a delay degradation library generation step, there is generated a delay degradation library containing delay parameters at the time when the LSI has operated for a predetermined period of time.Type: GrantFiled: December 5, 1997Date of Patent: April 4, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobufusa Iwanishi, Yoshiyuki Kawakami
-
Patent number: 6023394Abstract: A head slider supporting a read/write head for recording and reproducing information is disposed above a disk, i.e., an information recording medium. The head slider has on its surface facing the disk at least two transversely elongate dynamic pressure generating parts formed with their longer sides extended substantially perpendicularly to the rotating direction of the disk and arranged one behind the other in the rotating direction. The front dynamic pressure generating part is provided with a land of a length in the rotating direction of the disk greater than 10% and smaller than 50%. The land protrudes toward the disk and has a shoulder.Type: GrantFiled: March 9, 1999Date of Patent: February 8, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Jun Ito, Yoshiyuki Kawakami