Patents by Inventor Yosseff Levanoni
Yosseff Levanoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860863Abstract: A journal-based database may include items, e.g., organized in a table, associated with a journal. The journal may include a hash-chained set of blocks individually including data representing previous and/or current versions of the individual items. The database may receive a request to redact specific data from the database. The database may search the blocks to determine whether the specific data exists. When the specific data exists in a block of the journal, the database may redate the specific data in the identified block. The database may retain existing metadata of the block such that cryptographic verifiability of the hash-chained blocks may be preserved.Type: GrantFiled: June 30, 2022Date of Patent: January 2, 2024Assignee: Amazon Technologies, Inc.Inventors: Marc Bowes, Victoria Elizabeth Scearcy, Kritin Gokharu, Eric Justin Kraemer, Junaid Azad Mohammed, Abigail Marie Kuic, Robert McGregor Marrowstone, Steven Michael Hershey, Yosseff Levanoni, Omer Ronen
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Patent number: 11797521Abstract: A database system may associate functions with a database table. A request to associate a function with a table in a database system may be received. An association between the table and the function may be created. The function may include parameters that are determined from values within the table which are then invoked by a request to perform the function. The associated function may cause the collection of the values prior to performance of the function.Type: GrantFiled: June 30, 2020Date of Patent: October 24, 2023Assignee: Amazon Technologies, Inc.Inventors: Akshat Vig, Somasundaram Perianayagam, Colin Lazier, James Christopher Sorenson, Yosseff Levanoni, Stefano Stefani, Maximiliano Maccanti
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Patent number: 10635336Abstract: A distributed system may comprise a plurality of computing nodes, each of which may provide computing capacity for operating various computing services. The system may maintain a memory-based store of records representative of capacity available on the computing nodes. A record indicative of a computing node having a requested amount of capacity may be selected. The record may be modified to indicate that the computing node is a candidate for providing the requested amount of capacity. Upon receiving information confirming that the computing node has been configured to provide the requested capacity, the record may be modified to indicate that the computing node has committed to provide the requested capacity.Type: GrantFiled: December 16, 2016Date of Patent: April 28, 2020Assignee: Amazon Technologies, Inc.Inventors: Hao He, David Alan Lutz, Andrew Whitaker, Yosseff Levanoni
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Patent number: 10620916Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: GrantFiled: August 30, 2016Date of Patent: April 14, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9971710Abstract: Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.Type: GrantFiled: February 7, 2013Date of Patent: May 15, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Amit Kumar Agarwal, Yosseff Levanoni, Weirong Zhu
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Patent number: 9658880Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.Type: GrantFiled: March 18, 2013Date of Patent: May 23, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
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Publication number: 20160371061Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9430204Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: GrantFiled: November 19, 2010Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9411634Abstract: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.Type: GrantFiled: June 21, 2010Date of Patent: August 9, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Lingli Zhang, Yosseff Levanoni, David L. Detlefs, Sukhdeep S. Sodhi, Weirong Zhu
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Patent number: 9239803Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: August 10, 2015Date of Patent: January 19, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Publication number: 20160013966Abstract: Various embodiments enable a group of devices to be logically grouped together in what is referred to as a “device circle.” The devices in a device circle can be bound through static and dynamic bindings. In at least some embodiments, the device circle serves as a single abstract entity that does not necessarily expose its individual constituent devices. As such, communication and other functionality can take place with the device circle in a manner that does not divulge the identities, capabilities, or roles of the individual devices that make up the device circle.Type: ApplicationFiled: July 11, 2014Publication date: January 14, 2016Inventors: Shankar Vaidyanathan, Todd L. Paul, Yosseff Levanoni, Arvind Sethuraman, Weirong Zhu, Lingli Zhang
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Publication number: 20150347323Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 9104628Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: January 10, 2015Date of Patent: August 11, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Publication number: 20150186165Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a variable offset pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.Type: ApplicationFiled: March 17, 2015Publication date: July 2, 2015Inventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Patent number: 9047139Abstract: Software transactional memory (STM) primitives are provided that allow the results of prior open calls to be used by subsequent open calls either as-is or through another STM primitive that consumes the results of the previous invocation. The STM primitives are configured to ensure that the address of a shadow copy representing a memory location will not changed across a wide range of operations and thereby enable re-use of the shadow copy.Type: GrantFiled: June 27, 2008Date of Patent: June 2, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, David L. Detlefs, Michael M. Magruder, Vinod K. Grover
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Publication number: 20150127915Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: ApplicationFiled: January 10, 2015Publication date: May 7, 2015Inventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 8997066Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.Type: GrantFiled: December 27, 2010Date of Patent: March 31, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Patent number: 8990515Abstract: The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.Type: GrantFiled: June 14, 2011Date of Patent: March 24, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni
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Patent number: 8954995Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: October 1, 2008Date of Patent: February 10, 2015Assignee: Microsoft CorporationInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 8839214Abstract: A high level programming language provides an extensible set of transformations for use on indexable types in a data parallel processing environment. A compiler for the language implements each transformation as a map from indexable types to allow each transformation to be applied to other transformations. At compile time, the compiler identifies sequences of the transformations on each indexable type in data parallel source code and generates data parallel executable code to implement the sequences as a combined operation at runtime using the transformation maps. The compiler also incorporates optimizations that are based on the sequences of transformations into the data parallel executable code.Type: GrantFiled: June 30, 2010Date of Patent: September 16, 2014Assignee: Microsoft CorporationInventors: Paul F. Ringseth, Weirong Zhu, Rick Molloy, Charles D. Callahan, II, Yosseff Levanoni, Lingli Zhang