Abstract: According to an embodiment, a shift register parallelizes a serial data signal serving to transfer data including multiple symbols on the basis of a first clock. A first circuit generates, on the basis of the first clock, a second clock being a clock signal for transferring a parallel data signal having a width of the first number of bits. A first flip-flop group sequentially fetches data of the first number of bits from the serial data signals parallelized by the shift register on the basis of the second clock. The first flip-flop group then outputs the fetched data of the first number of bits as a parallel data signal. A second circuit adjusts a phase of the second clock such that the first flip-flop group fetches data of the first number of bits beginning with bit data located at a head of each symbol of the multiple symbols.

Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.

Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.

Abstract: According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

Abstract: According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.