Patents by Inventor You Yang Ong

You Yang Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8803299
    Abstract: A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventor: You Yang Ong
  • Patent number: 8546929
    Abstract: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 1, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Patent number: 8415786
    Abstract: A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 9, 2013
    Assignee: STATS ChipPac Ltd.
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Publication number: 20120187555
    Abstract: A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.
    Type: Application
    Filed: April 3, 2012
    Publication date: July 26, 2012
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Patent number: 8163604
    Abstract: An integrated circuit package system includes a conductive substrate. A heat sink and a plurality of leads are etched in the substrate to define a conductive film connecting the heat sink and the plurality of leads to maintain their spatial relationship. A die is attached to the heat sink and wire bonded to the plurality of leads. An encapsulant is formed over the die, the heat sink, and the plurality of leads. The conductive film is etched away to expose the encapsulant and the bottom surfaces of the heat sink and the plurality of leads. Wave soldering is used to form solder on at least the plurality of leads. Multiple heat sinks and hanging leads are provided.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: April 24, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: You Yang Ong, Cheong Chiang Ng, Suhairi Mohmad
  • Patent number: 8164182
    Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 24, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Patent number: 8093694
    Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: January 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: You Yang Ong
  • Patent number: 8067832
    Abstract: A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Publication number: 20110079899
    Abstract: A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 7, 2011
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Patent number: 7868434
    Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7859098
    Abstract: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Publication number: 20100176497
    Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 15, 2010
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7718472
    Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: May 18, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7598600
    Abstract: The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 6, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Wai Kwong Tang, You Yang Ong, Kuan Ming Kan, Larry Lewellen
  • Publication number: 20090179312
    Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.
    Type: Application
    Filed: March 24, 2009
    Publication date: July 16, 2009
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7557432
    Abstract: The present invention provides a thermally enhanced power semiconductor package system comprising providing a power semiconductor die, forming an upper lead frame on the power semiconductor die and forming a lower lead frame below the power semiconductor die, wherein the upper lead frame and the lower lead frame are provided in an offset configuration relative to each other to provide two heat dissipation paths.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: July 7, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Wai Kwong Tang, You Yang Ong, Kuan Ming Kan, Larry Lewellen
  • Patent number: 7535086
    Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 19, 2009
    Assignee: STATS ChipPac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7443018
    Abstract: An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: October 28, 2008
    Assignees: Stats Chippac Ltd., Orthodyne Electronics Corporation
    Inventors: You Yang Ong, Kwang Yong Chung, Mohd Helmy Bin Ahmad, Garrett L. Wong, Christoph B. Luechinger
  • Publication number: 20080029858
    Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.
    Type: Application
    Filed: August 3, 2006
    Publication date: February 7, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Publication number: 20070246813
    Abstract: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.
    Type: Application
    Filed: April 19, 2006
    Publication date: October 25, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: You Yang Ong, Dioscoro Merilo, Seng Guan Chow