Patents by Inventor Youichi Yamamoto

Youichi Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11759297
    Abstract: Provided is a reference denture alignment jig which guides reference dentures into an oral cavity or to an articulator in which upper and lower edentulous jaw models are fixed, and aligns the reference dentures in the oral cavity or in the articulator in which upper and lower edentulous jaw models are fixed, the jig having a reference denture holding portion for holding reference dentures.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 19, 2023
    Assignee: TOKUYAMA DENTAL CORPORATION
    Inventors: Tatsuya Yamazaki, Kei Nakashima, Youichi Yamamoto, Hitoshi Motohashi
  • Publication number: 20210137652
    Abstract: Provided is a reference denture alignment jig which guides reference dentures into an oral cavity or to an articulator in which upper and lower edentulous jaw models are fixed, and aligns the reference dentures in the oral cavity or in the articulator in which upper and lower edentulous jaw models are fixed, the jig having a reference denture holding portion for holding reference dentures.
    Type: Application
    Filed: May 10, 2018
    Publication date: May 13, 2021
    Applicant: TOKUYAMA DENTAL CORPORATION
    Inventors: Tatsuya YAMAZAKI, Kei NAKASHIMA, Youichi YAMAMOTO, Hitoshi MOTOHASHI
  • Patent number: 10381444
    Abstract: To improve the performance of a semiconductor device, there is provided with a manufacturing method of a semiconductor device including a step of removing an oxide film formed on the surface of a silicon carbide substrate including the inner wall of a trench, before forming the hydrogen annealing.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Youichi Yamamoto
  • Publication number: 20180145137
    Abstract: To improve the performance of a semiconductor device, there is provided with a manufacturing method of a semiconductor device including a step of removing an oxide film formed on the surface of a silicon carbide substrate including the inner wall of a trench, before forming the hydrogen annealing.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 24, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Youichi YAMAMOTO
  • Patent number: 9478547
    Abstract: Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 25, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Masashige Moritoki, Toshiji Taiji, Youichi Yamamoto
  • Patent number: 9379178
    Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: June 28, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
  • Publication number: 20160071850
    Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.
    Type: Application
    Filed: November 3, 2015
    Publication date: March 10, 2016
    Inventors: Misato SAKAMOTO, Yoshitake KATO, Youichi YAMAMOTO, Hitoshi KASAI, Satoshi ITOU
  • Patent number: 9255011
    Abstract: The present invention relates to a method for producing lithium carbonate, which is important as a raw material of a lithium ion battery and the like, from brine resources. More specifically, the invention relates to a method for producing lithium carbonate, in which carbon dioxide gas obtained by calcining limestone is introduced, in the presence of ammonia, into a concentrated brine, which is prepared from a lithium-containing brine as a raw material through an evaporative concentrating step, a desulfurizing step and an electrodialysis step, thereby depositing lithium carbonate crystals, and the crystals thus deposited are recovered through solid-liquid separation.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignees: NITTETSU MINING CO., LTD., TOYO ENGINEERING CORPORATION, SUMITOMO CORPORATION
    Inventors: Masanobu Kawata, Hirohumi Tanaka, Kohei Mitsuhashi, Ryo Kawarabuki, Youichi Yamamoto, Keita Kamiyama, Atsushi Moriya, Norifumi Sakai
  • Publication number: 20150372074
    Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 24, 2015
    Inventors: Youichi YAMAMOTO, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
  • Publication number: 20150357335
    Abstract: Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).
    Type: Application
    Filed: June 3, 2015
    Publication date: December 10, 2015
    Inventors: Hiroyuki Kunishima, Masashige Moritoki, Toshiji Taiji, Youichi Yamamoto
  • Patent number: 9209189
    Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Yoshitake Kato, Youichi Yamamoto, Hitoshi Kasai, Satoshi Itou
  • Publication number: 20150270271
    Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Misato SAKAMOTO, Yoshitake KATO, Youichi YAMAMOTO, Hitoshi KASAI, Satoshi ITOU
  • Patent number: 9142609
    Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
  • Patent number: 8987148
    Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Yoshitake Katou, Youichi Yamamoto, Takashi Kyouno, Chikara Yamamoto, Terukazu Motosawa, Mitsuo Maeda, Hiroshi Itou
  • Patent number: 8940601
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Patent number: 8607539
    Abstract: Provided are an organopolysiloxane composition for producing a rope structure excellent in fatigue resistance, a rope structure using the same, and a process for producing the rope structure. The organopolysiloxane composition comprises an organopolysiloxane having an average polymerization degree of 50,000 to 200,000 and represented by the following formula (I): wherein X1, X2, X3 and X4 are the same or different, each independently representing —H, —OH, —COOH, —R, —NH2, —ROH, —RCOOH, or —RNH2; R representing an alkyl group or an aryl group; and each of m and n independently denotes an integer of not less than 1. The organopolysiloxane composition is applied to liquid crystalline polymer filaments in the process of producing the rope structure from the filaments.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: December 17, 2013
    Assignee: Kuraray Co., Ltd.
    Inventors: Akihiro Uehata, Yuji Ogino, Mariko Mine, Youichi Yamamoto, Masao Kawamoto
  • Publication number: 20130251610
    Abstract: The present invention relates to a method for producing lithium carbonate, which is important as a raw material of a lithium ion battery and the like, from brine resources. More specifically, the invention relates to a method for producing lithium carbonate, in which carbon dioxide gas obtained by calcining limestone is introduced, in the presence of ammonia, into a concentrated brine, which is prepared from a lithium-containing brine as a raw material through an evaporative concentrating step, a desulfurizing step and an electrodialysis step, thereby depositing lithium carbonate crystals, and the crystals thus deposited are recovered through solid-liquid separation.
    Type: Application
    Filed: November 29, 2012
    Publication date: September 26, 2013
    Applicants: NITTETSU MINING CO., LTD., SUMITOMO CORPORATION, TOYO ENGINEERING CORPORATION
    Inventors: Masanobu KAWATA, Hirohumi TANAKA, Kohei MITSUHASHI, Ryo KAWARABUKI, Youichi YAMAMOTO, Keita KAMIYAMA, Atsushi MORIYA, Norifumi SAKAI
  • Publication number: 20130011994
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 10, 2013
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Publication number: 20120238043
    Abstract: With the stage kept in an as-heated state, the semiconductor wafer is placed over the stage (step S10). Then, with the elapse of first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside the adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over the protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 20, 2012
    Inventors: Misato SAKAMOTO, Yoshitake KATOU, Youichi YAMAMOTO, Takashi KYOUNO, Chikara YAMAMOTO, Terukazu MOTOSAWA, Mitsuo MAEDA, Hiroshi ITOU
  • Patent number: D897539
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 29, 2020
    Assignee: Tokuyama Dental Corporation
    Inventors: Tatsuya Yamazaki, Kei Nakashima, Youichi Yamamoto, Hitoshi Motohashi