Patents by Inventor You-Mee HYUN
You-Mee HYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908417Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.Type: GrantFiled: April 25, 2022Date of Patent: February 20, 2024Assignee: Samsung Display Co., Ltd.Inventors: Kang Nam Kim, You Mee Hyun, Beom Jun Kim, Jong Hwan Lee, Sung Hoon Lim, Duc Han Cho
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Publication number: 20230252932Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 11631359Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: March 22, 2021Date of Patent: April 18, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20220254310Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Inventors: Kang Nam KIM, You Mee HYUN, Beom Jun KIM, Jong Hwan LEE, Sung Hoon LIM, Duc Han CHO
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Patent number: 11315495Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.Type: GrantFiled: April 14, 2017Date of Patent: April 26, 2022Assignee: Samsung Display Co., Ltd.Inventors: Kang Nam Kim, You Mee Hyun, Beom Jun Kim, Jong Hwan Lee, Sung Hoon Lim, Duc Han Cho
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Publication number: 20210384283Abstract: A display device includes: a first base on which a display area and a non-display area are defined; a light-emitting element on the first base and in the display area; a second base facing the first base and above the light-emitting element; a color filter on a surface of the second base that faces the first base and overlapping the light-emitting element; a wavelength conversion pattern on the color filter; a sealing member in the non-display area between the first base and the second base; and a sink pattern in the non-display area, wherein the sink pattern is between the sealing member and the display area when viewed from a plan view.Type: ApplicationFiled: June 3, 2021Publication date: December 9, 2021Inventors: Hyung Gi JUNG, Ki Hwan KIM, Beom Jin KIM, Soon Chang YEON, Sung Hyun LEE, Jae Min LEE, Jae Young LEE, You Mee HYUN
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Publication number: 20210209997Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 10957242Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: September 25, 2019Date of Patent: March 23, 2021Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20200020269Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 10467946Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: January 26, 2017Date of Patent: November 5, 2019Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20180018920Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.Type: ApplicationFiled: April 14, 2017Publication date: January 18, 2018Inventors: Kang Nam Kim, You Mee Hyun, Beom Jun Kim, Jong Hwan Lee, Sung Hoon Lim, Duc Han Cho
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Patent number: 9865212Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.Type: GrantFiled: June 18, 2015Date of Patent: January 9, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Duc-Han Cho, Kang Nam Kim, Beom Jun Kim, You Mee Hyun
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Publication number: 20170140698Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 9589519Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: March 10, 2014Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20160171950Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.Type: ApplicationFiled: June 18, 2015Publication date: June 16, 2016Inventors: Duc-Han CHO, Kang Nam KIM, Beom Jun KIM, You Mee HYUN
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Patent number: 9218074Abstract: A gate drive circuit in which multiple stages are connected together one after each other. An n-th stage includes a pull-up part, a carry part, a pull-down part, a switching part, a first maintaining part and a second maintaining part. The pull-up part outputs a high voltage of a first clock signal. The carry part outputs a high voltage of the first clock signal. The pull-down part pulls-down the n-th gate signal into a first low voltage. The switching part outputs a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal. The first maintaining part maintains the n-th gate signal at the first low voltage in response to the first signal. The second maintaining part maintains the n-th gate signal at the first low voltage in response to a second signal.Type: GrantFiled: December 19, 2012Date of Patent: December 22, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Duc-Han Cho, Kang-Nam Kim, Jae-Hoon Lee, You-Mee Hyun, Jong-Woong Chang, Yun Heo
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Patent number: 9203395Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.Type: GrantFiled: June 28, 2013Date of Patent: December 1, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Kang Nam Kim, Duc-Han Cho, You Mee Hyun, Jeong-Il Kim, Jong Woong Chang
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Patent number: 8957882Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.Type: GrantFiled: November 9, 2011Date of Patent: February 17, 2015Assignee: Samsung Display Co., Ltd.Inventors: Jae-Hoon Lee, Young-Su Kim, Whee-Won Lee, Jun-Yong Song, Yu-Han Bae, You-Mee Hyun
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Publication number: 20140267214Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: March 10, 2014Publication date: September 18, 2014Applicant: Samsung Display Co., Ltd.Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Publication number: 20140204009Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.Type: ApplicationFiled: June 28, 2013Publication date: July 24, 2014Inventors: Kang Nam Kim, Duc-Han Cho, You Mee Hyun, Jeong-II Kim, Jong Woong Chang