Patents by Inventor Youn-Joung Cho
Youn-Joung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12113035Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.Type: GrantFiled: November 1, 2023Date of Patent: October 8, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Su Lee, Hong Sik Chae, Youn Soo Kim, Tae Kyun Kim, Youn Joung Cho
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Publication number: 20240213017Abstract: A method of manufacturing an integrated circuit device, the method including forming a doped silicon oxide film on a substrate by supplying, onto the substrate, a silicon precursor, an oxidant, and at least two dopant sources including dopant elements that are different from each other such that the doped silicon oxide film includes at least two dopant elements; forming a vertical hole in the doped silicon oxide film by dry-etching the doped silicon oxide film; and forming a vertical structure in the vertical hole, wherein the silicon precursor includes a monosilane compound, a disilane compound, a siloxane compound, or a combination thereof, and the silicon precursor includes a Si—H functional group, and a C1-C10 oxy group or a C1-C10 organoamino group.Type: ApplicationFiled: July 31, 2023Publication date: June 27, 2024Inventors: Younghun SUNG, Sunhye HWANG, Sangho RHA, Seungjae SIM, Younseok CHOI, Byungkeun HWANG, Youn Joung CHO
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Patent number: 11929389Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: May 19, 2021Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Publication number: 20240079355Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.Type: ApplicationFiled: November 1, 2023Publication date: March 7, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-su LEE, Hong Sik CHAE, Youn Soo KIM, Tae Kyun KIM, Youn Joung CHO
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Publication number: 20240071810Abstract: Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device comprises forming a first layer which has a first surface, does not comprise an acid, and comprises a metal material; forming, on the first layer, a second layer which comprises a trench exposing the first surface, has a second surface intersecting the first surface within the trench, and comprises an acid and an organic material; providing a first precursor comprising an alkoxy group and silicon; and forming a third layer comprising silicon oxide on the second surface within the trench. The third layer is in contact with a portion of the first surface within the trench.Type: ApplicationFiled: May 5, 2023Publication date: February 29, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Eun Hyea KO, Hoon Han, Byung Keun Hwang, Young Hun Sung, Youn Joung Cho
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Patent number: 11901191Abstract: An atomic layer etching method capable of precisely etching a metal thin film at units of atomic layer from a substrate including the metal thin film, includes forming a metal layer on a substrate, and etching at least a portion of the metal layer. The etching at least a portion of the metal layer includes at least one etching cycle. The at least one etching cycle includes supplying an active gas onto the metal layer, and supplying an etching support gas after supplying the active gas. The etching support gas is expressed by the following general formula wherein each of R1, R2, R3, R4 and R5 independently includes hydrogen or a C1-C4 alkyl group, and N is nitrogen.Type: GrantFiled: November 26, 2021Date of Patent: February 13, 2024Assignees: Samsung Electronics Co., Ltd., DNF Co., Ltd.Inventors: Eun Hyea Ko, Hee Yeon Jeong, Jun Hee Cho, Gyu-Hee Park, Joong Jin Park, Byeong Il Yang, Youn Joung Cho, Ji Yu Choi
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Patent number: 11848287Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.Type: GrantFiled: September 9, 2021Date of Patent: December 19, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-su Lee, Hong Sik Chae, Youn Soo Kim, Tae Kyun Kim, Youn Joung Cho
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Publication number: 20230282475Abstract: A semiconductor device manufacturing method includes providing a first layer having a first surface, providing a second layer including a trench that exposes the first surface, onto the first layer, forming a first polymer layer that fills the trench, and performing a heat treatment process on the first polymer layer to form a second polymer layer. A second surface of the second layer is exposed by the trench, the first polymer layer includes a first portion being in contact with the first surface, and a second portion being in contact with the second surface, when the heat treatment process is performed, the first portion of the first polymer layer is decomposed, when the heat treatment process is performed, the second portion of the first polymer layer is cross-linked to form the second polymer layer, and physical properties of the first layer are different from physical properties of the second layer.Type: ApplicationFiled: January 19, 2023Publication date: September 7, 2023Inventors: Eun Hyea KO, Hoon HAN, Byung Keun HWANG, Jae Woon KIM, Jeong Ho MUN, Younghun SUNG, Hyun-Ji SONG, Youn Joung CHO
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Publication number: 20230220213Abstract: Compositions for manufacturing a thin film are provided. The compositions may include a compound having a structure of Chemical Formula 1: M may be strontium (Sr) or barium (Ba), X1 and X2 may each independently be oxygen (O) or a substituted or unsubstituted alkylamino group having 1 to 5 carbon atoms, R1 and R2 may each independently be a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms or a substituted or unsubstituted perfluoro alkyl group having 1 to 5 carbon atoms, R3 may be hydrogen or a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, L may be a substituted or unsubstituted polyether having 1 to 6 oxygen atoms, or a substituted or unsubstituted polyamine having 1 to 6 nitrogen atoms, or a substituted or unsubstituted polyetheramine having 1 to 6 oxygen atoms or nitrogen atoms, and n may be an integer of 1 to 6.Type: ApplicationFiled: December 22, 2022Publication date: July 13, 2023Applicant: ADEKA CORPORATIONInventors: JAE WOON KIM, Seung-min Ryu, Haruyoshi Sato, Kazuya Saito, Masayuki Kimura, Takahiro Yoshii, Tsubasa Shiratori, Min Jae Sung, Gyu-Hee Park, Youn Joung Cho
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Publication number: 20230142732Abstract: The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.Type: ApplicationFiled: November 7, 2022Publication date: May 11, 2023Inventors: Eun Hyea KO, Hoon HAN, Byung Keun HWANG, Jeong Ho MUN, Hyun-Ji SONG, Youn Joung CHO
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Publication number: 20220375760Abstract: An atomic layer etching method capable of precisely etching a metal thin film at units of atomic layer from a substrate including the metal thin film, includes forming a metal layer on a substrate, and etching at least a portion of the metal layer. The etching at least a portion of the metal layer includes at least one etching cycle. The at least one etching cycle includes supplying an active gas onto the metal layer, and supplying an etching support gas after supplying the active gas. The etching support gas is expressed by the following general formula wherein each of R1, R2, R3, R4 and R5 independently includes hydrogen or a C1-C4 alkyl group, and N is nitrogen.Type: ApplicationFiled: November 26, 2021Publication date: November 24, 2022Applicant: DNF CO., LTD.Inventors: EUN HYEA KO, HEE YEON JEONG, JUN HEE CHO, GYU-HEE PARK, JOONG JIN PARK, BYEONG IL YANG, YOUN JOUNG CHO, JI YU CHOI
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Publication number: 20220260212Abstract: A composition comprising acetylene fluid at least partially solubilized in an improved solvent is described. The improved solvents exhibit non-toxicity and are further characterized by low vapor pressures to minimize solvent carryover during delivery of the acetylene fluid, while retaining suitable acetylene solubilizing capacity.Type: ApplicationFiled: February 9, 2022Publication date: August 18, 2022Inventors: Ashwini K. Sinha, Xuemei Song, William S. Kane, Youn-Joung Cho, Wonwoong Chung, Yeonock Han
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Publication number: 20220093532Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.Type: ApplicationFiled: September 9, 2021Publication date: March 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-su LEE, Hong Sik CHAE, Youn Soo KIM, Tae Kyun KIM, Youn Joung CHO
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Publication number: 20210380622Abstract: Materials for fabricating a thin film that has improved quality and productivity are provided. The materials may include a Group 5 element precursor of formula (1): M1 may be a Group 5 element, each of R1 to R10 independently may be a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, or f7onnula (2), R11 may be a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, and L1 may be an alkyl group, an alkylamino group, an alkoxy group or an alkylsilyl group, each of which may have 1 to 5 carbon atoms and may be substituted or unsubstituted. Formula (2) may have a structure of Each of Ra to Rc independently may be a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms.Type: ApplicationFiled: March 29, 2021Publication date: December 9, 2021Inventors: Seung-Min Ryu, Gyu-Hee Park, Youn Joung Cho, Kazuki Harano, Takanori Koide, Wakana Fuse, Yoshiki Manabe, Yutaro Aoki, Hiroyuki Uchiuzou, Kazuya Saito
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Publication number: 20210273039Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Youn-soo KIM, Seung-min RYU, Chang-su WOO, Hyung-suk JUNG, Kyu-ho CHO, Youn-joung CHO
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Patent number: 11062940Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.Type: GrantFiled: June 17, 2019Date of Patent: July 13, 2021Assignees: Samsung Electronics Co., Ltd., DNF Co., Ltd.Inventors: Chang-Woo Sun, Ji-Eun Yun, Jae-Soon Lim, Youn-Joung Cho, Myong-Woon Kim, Kang-yong Lee, Sang-Ick Lee, Sung-Woo Cho
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Patent number: 11043553Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: July 24, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Patent number: 10923341Abstract: A method of forming an oxide layer, the method including forming a first material layer on a semiconductor substrate, the first material layer including a polysiloxane material, wherein, from among Si—H1, Si—H2, and Si—H3 bonds included in the polysiloxane material, a percentage of Si—H2 bonds ranges from about 40% to about 90%, performing a first annealing process on the first material layer in an inert atmosphere, and performing a second annealing process on the first material layer in an oxidative atmosphere.Type: GrantFiled: March 5, 2019Date of Patent: February 16, 2021Assignees: Samsung Electronics Co., Ltd., Adeka CorporationInventors: Jin-wook Park, Tae-jin Yim, Youn-joung Cho, Hiroshi Morita, Yasuhisa Furihata
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Patent number: 10913754Abstract: A lanthanum compound, a method of synthesizing a thin film, and a method of manufacturing an integrated circuit device, the compound being represented by Formula 1 below, wherein, in Formula 1, R1 is a hydrogen atom or a C1-C4 linear or branched alkyl group, R2 and R3 are each independently a hydrogen atom or a C1-C5 linear or branched alkyl group, at least one of R2 and R3 being a C3-C5 branched alkyl group, and R4 is a hydrogen atom or a C1-C4 linear or branched alkyl group.Type: GrantFiled: January 18, 2019Date of Patent: February 9, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., ADEKA CORPORATIONInventors: Gyu-hee Park, Youn-soo Kim, Jae-soon Lim, Youn-joung Cho, Kazuki Harano, Haruyoshi Sato, Tsubasa Shiratori, Naoki Yamada
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Patent number: 10882873Abstract: A tin compound, tin precursor compound for atomic layer deposition (ALD), a method of forming a tin-containing material film, and a method of synthesizing a tin compound, the tin compound being represented by Chemical Formula (I): wherein R1, R2, Q1, Q2, Q3, and Q4 are each independently a C1 to C4 linear or branched alkyl group.Type: GrantFiled: January 16, 2019Date of Patent: January 5, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., DNF Co., Ltd.Inventors: Seung-min Ryu, Youn-soo Kim, Jae-soon Lim, Youn-joung Cho, Myong-woon Kim, Kang-yong Lee, Sang-ick Lee, Sang-yong Jeon