Abstract: Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Abstract: A method of writing partial page data in a non-volatile memory device includes, reading data from a second block when the size of a last page of data to be written in a page of a first block is smaller than a size of the page of the first block, wherein a size of the read data is given by the size of the page of the first block minus the size of the last page of data; storing together data of the last page and the data read from the second block in a buffer; and writing the data stored in the buffer in the first block.

Abstract: Provided is a data writing method of copying data having logical pages prior to logical pages of data to write from a data block used in non-volatile memory device. The data writing method includes copying data having logical pages prior to a logical page of data to write from a second block to a first block, and writing the data to write in a page next to the copied prior logical pages.

Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.

Abstract: An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

Abstract: A debugging method employed by a memory card includes performing an initialization operation of the memory card, determining whether an error has occurred in the initialization operation, and upon the occurrence of an error during the initialization operation, executing an error control program when a first control command is input. The execution of the error control program performing an interrupt service routine, and jumping to a system initialization routine after the interrupt service routine is performed.

Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: A lead assembly including a connector connecting structure having a plurality of separable portions and a plurality of leads. Each of the leads defined that they have a first end, a second end, a lead axis defined by the first and the second end, and an offset portion disposed between the first end and the second end. The offset portion being offset from the lead axis and adapted to be displaced downwardly with respect to the lead axis and bonded to a contact. The leads are preferably integral with the connecting structure. The connecting structure may be arranged outwardly of the leads, or may include parts interdispersed between groups of leads. The groups of leads may or may not correspond to individual units incorporating a microelectronic element.

Abstract: A method for calibrating a laser transmitter includes (a) detecting an eye diagram of an output from the laser transmitter, (b) determining if the eye diagram is acceptable, (c) if the eye diagram is not acceptable, changing a value of a control signal in the laser transmitter, wherein the control signal sets an amplitude characteristic of a limiting amplifier coupled to a laser driver in the laser transmitter, and (d) repeating steps (a), (b), and (c) until the eye diagram is acceptable.

Abstract: A laser transmitter includes an input stage generating an input signal to a limiting amplifier, the limiting amplifier generating an input signal to a laser driver, and the laser driver generating an input signal to a light source. The limiting amplifier has a control terminal for receiving a control signal that sets an amplitude characteristic of the input signal to the laser driver. The amplitude characteristic may be a common-mode or a peak amplitude of the input signal to the laser driver.

Abstract: A method of making a stacked microelectronic assembly includes providing a flexible substrate having first and second ends, the flexible substrate having a plurality of attachment sites located between the first and second ends thereof including a first one of the attachment sites located adjacent the first end of the flexible substrate, the flexible substrate including conductive terminals accessible at a surface of the flexible substrate and wiring connected to the terminals, providing a compliant layer over the first attachment site, assembling a plurality of microelectronic elements over the attachment sites, wherein a first one of the microelectronic elements engages the compliant layer and is movable relative to the flexible substrate, electrically interconnecting the microelectronic elements and the wiring, folding the flexible substrate and stacking at least some of the microelectronic elements in generally vertical alignment with one another so that the first one of the microelectronic elements engag

Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.

Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.