Patents by Inventor Young-Gun Ko

Young-Gun Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141312
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin. The semiconductor device includes a second insulating material in a second fin. The first and second insulating materials have different respective sizes. For example, in some embodiments, the first and second insulating materials have different respective widths and/or depths in the first and second fins, respectively.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Jeon, Young-Gun Ko, Gi-Gwan Park, Je-Min Yoo
  • Publication number: 20170110456
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin. The semiconductor device includes a second insulating material in a second fin. The first and second insulating materials have different respective sizes. For example, in some embodiments, the first and second insulating materials have different respective widths and/or depths in the first and second fins, respectively.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 20, 2017
    Inventors: Ho-Jin Jeon, Young-Gun Ko, Gi-Gwan Park, Je-Min Yoo
  • Patent number: 9240481
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Patent number: 9209177
    Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Young-Gun Ko
  • Publication number: 20150251160
    Abstract: The present invention relates to an adsorbent including a hierarchically porous silica monolith, and particularly, to an adsorbent for adsorbing or separating carbon dioxide in air or heavy metals in an aqueous solution, in which an amino group is covalently bonded to the silica monolith. Further, the present invention relates to a method for preparing the adsorbent including a hierarchically porous silica monolith, and particularly, to a method for preparing an adsorbent for adsorbing or separating carbon dioxide in air or heavy metals in an aqueous solution, in which an amino group is covalently bonded to the silica monolith.
    Type: Application
    Filed: August 28, 2014
    Publication date: September 10, 2015
    Inventors: Ung Su CHOI, Young Gun KO, Hyun Jeong LEE, Hyun Chul OH, Tae Gu DO
  • Publication number: 20150123176
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Patent number: 8962435
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20150024565
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Patent number: 8884298
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Publication number: 20140203362
    Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.
    Type: Application
    Filed: March 4, 2013
    Publication date: July 24, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hae KIM, Jong-Shik YOON, Young-Gun KO
  • Publication number: 20130341631
    Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
    Type: Application
    Filed: March 14, 2013
    Publication date: December 26, 2013
    Inventors: Shigenobu Maeda, Hidenobu Fukutome, Young-Gun Ko, Joo-Hyun Jeong
  • Patent number: 7618868
    Abstract: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: November 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yoon Yoo, Young-gun Ko
  • Patent number: 7612414
    Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: November 3, 2009
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.
    Inventors: Xiangdong Chen, Jun Jung Kim, Young Gun Ko, Jae-Eun Park, Haining S. Yang
  • Patent number: 7576407
    Abstract: Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Gun Ko, Ja-Hum Ku, Minchul Sun, Robert Weiser
  • Patent number: 7569456
    Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: August 4, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-gun Ko, Chang-bong Oh
  • Patent number: 7541234
    Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: June 2, 2009
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG
    Inventors: Chong Kwang Chang, Haoren Zhuang, Matthias Lipinski, Shailendra Mishra, O Sung Kwon, Tjin Tjin Tjoa, Young Gun Ko
  • Patent number: 7531401
    Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 12, 2009
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.
    Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
  • Publication number: 20080237737
    Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONINCS CO., LTD.
    Inventors: Xiangdong Chen, Jun Jung Kim, Young Gun Ko, Jae-Eun Park, Haining S. Yang
  • Publication number: 20080191284
    Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.
    Type: Application
    Filed: February 8, 2007
    Publication date: August 14, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
  • Publication number: 20080124859
    Abstract: Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as a boron-doped silicon nitride layer or an electrically insulating layer that is doped with germanium and/or fluorine. The electrically insulating layer is etched-back to define first sidewall spacers on the first gate electrode and second sidewall spacers on the second gate electrode. P-type source and drain region dopants are then implanted into the semiconductor substrate, using the first sidewall spacers as a first implant mask. The second sidewall spacers on the second gate electrode are then etched back to reduce their lateral dimensions.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: Min Chul Sun, Jong Ho Yang, Young Gun Ko, Ja Hum Ku, Jae Eon Park, Jeong Hwan Yang, Christopher Vincent Baiocco, Gerald Leake