Patents by Inventor Young-Ho Yang

Young-Ho Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150640
    Abstract: There is provide an image encoding method including transforming an image block into a first latent representation based on an invertible neural network, transforming the first latent representation into a second latent representation based on a non-invertible neural network, estimating a probability distribution of the first latent representation, and performing entropy encoding on the first latent representation based on the probability distribution by using an entropy encoder.
    Type: Application
    Filed: June 14, 2024
    Publication date: May 8, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Eon KIM, Won Hee Lee, Jun Hyuk Kim, Jeong Won Kim, Young Hun Sung, Won Seop Song, Jung Yeop Yang, Do Kwan Oh, Sung Ho Jun, Woo Suk Choi, Jong Seong Choi
  • Publication number: 20250113808
    Abstract: The present invention relates to a brain-metastatic lung cancer cell line and a use of Noggin as a marker for brain metastasis of lung cancer. In the present invention, a brain metastatic lung cancer cell line with optimized characteristics for brain metastasis was established by repeatedly transplanting the lung cancer cell line through the carotid artery. In addition, in the brain metastatic lung cancer cell line, the expressions of Noggin protein and its mRNA are reduced, confirming that the motility and invasiveness of cells are reduced and adhesion increased. Therefore, the Noggin protein or its gene is expected to be useful as a biomarker for diagnosis of brain metastasis of lung cancer and its target therapy.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 10, 2025
    Inventors: Seung Ho YANG, Young-Ho AHN, Jung Eun LEE
  • Patent number: 12270512
    Abstract: Disclosed is a corner structure (100) of a liquefied gas storage tank, wherein the corner structure is installed at a corner of a storage tank for loading liquefied gas and supports sealing walls (51, 52) that prevent leakage of the liquefied gas. The corner structure (100) may include: two insulation members (110) arranged on the inner surface of a hull structure so as to be oriented in different directions; and mobile members (130) which are installed on the respective insulation members (110) and to which the sealing walls (51, 52) are joined. The mobile members (130) may be slidably coupled to the insulation members 110, and a plurality of the mobile members (130) may be arranged spaced apart from each other in a straight line on one of the insulation members.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 8, 2025
    Assignee: KOREA GAS CORPORATION
    Inventors: Ki Ho Yim, Hae Chul Han, Young Chul Yang, Heung Seok Seo, Youngkyun Kim, Kyo Kook Jin, Youngkeun Yoon
  • Patent number: 12255237
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: March 18, 2025
    Assignee: SK hynix Inc.
    Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
  • Patent number: 12249284
    Abstract: Provided are a pixel circuit and a display device having the pixel circuit. The pixel circuit includes an organic light emitting diode, a switching transistor, a storage capacitor, and a driving transistor. The switching transistor is turned off when a scan signal has a first voltage and turned on when the scan signal has a second voltage. The storage capacitor stores a data voltage when the switching transistor is turned on in response to the scan signal. The driving transistor is electrically connected with the organic light emitting diode between a high power supply voltage and a low power supply voltage to provide a driving current to the organic light emitting diode, and includes a first bottom gate electrode that is provided with the first voltage. The driving current corresponds to the data voltage stored in the storage capacitor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 11, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung-Mi Choi, Young-In Hwang, Eung Taek Kim, Yong Ho Yang, Joo Hyeon Jo, Seong Baik Chu
  • Patent number: 12227676
    Abstract: Provided is an adhesive composition including lysine, alpha ketoglutaric acid, and water, wherein the lysine and the alpha ketoglutaric acid are present in the form of an aqueous salt solution and do not form precipitates in the aqueous solution.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 18, 2025
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Ji Ho Hwang, Young Lyeol Yang, Chang Yub Oh, Chang Suk Lee, Kyung Su Na, Jun Ok Moon
  • Publication number: 20250024698
    Abstract: An object of the present invention is to provide a material for organic EL elements, the material being excellent in hole injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability. Another object of the present invention is to provide an organic EL element having high efficiency, a low driving voltage, and a long lifespan, by combining the aforementioned material with various materials for organic EL elements, the materials being excellent in hole/electron injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability, such that the properties of the individual materials can be effectively exhibited.
    Type: Application
    Filed: August 1, 2022
    Publication date: January 16, 2025
    Applicants: HODOGAYA CHEMICAL CO., LTD., SFC CO., LTD.
    Inventors: Junichi IZUMIDA, Sang-Won KO, Bong-Hyang LEE, Jung-Ho RYU, Jin-ho LEE, Kouki KASE, Shuichi HAYASHI, Se-Jin LEE, Tae-Jung YU, Young-Tae CHOI, Sung-Hoon JOO, Byung-Sun YANG, Ji-Hwan KIM, Bong-Ki SHIN
  • Patent number: 11935926
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 19, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Publication number: 20240006495
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: SK hynix Inc.
    Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
  • Patent number: 11799003
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
  • Patent number: 11588026
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: February 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Publication number: 20220181455
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Application
    Filed: April 15, 2021
    Publication date: June 9, 2022
    Applicant: SK hynix Inc.
    Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
  • Patent number: 11296188
    Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Hee Soo Kim, Young Ho Yang, Chang Soo Lee, Wan Sup Shin
  • Publication number: 20210036109
    Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.
    Type: Application
    Filed: February 14, 2020
    Publication date: February 4, 2021
    Applicant: SK hynix Inc.
    Inventors: Hee Soo KIM, Young Ho YANG, Chang Soo LEE, Wan Sup SHIN
  • Publication number: 20200388686
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Application
    Filed: January 13, 2020
    Publication date: December 10, 2020
    Inventors: Hyeng-Woo EOM, Jung-Myoung SHIM, Young-Ho YANG, Kwang-Wook LEE, Won-Joon CHOI
  • Patent number: 10714499
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Publication number: 20190319045
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 10373973
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Publication number: 20190081066
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: April 24, 2018
    Publication date: March 14, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 9726656
    Abstract: Disclosed herein is an experiment apparatus for estimating ground surface deformation during gas hydrate recovery. The experiment apparatus may include: a high-pressure cell having a space in which a sample containing gas hydrate is stored; a pressurizing member mounted to move in one direction in the high-pressure cell, and moved to pressurize the sample stored in the space, wherein the surface of the sample is observed along the longitudinal direction of the pressurizing member through the pressurizing member from outside; and a recovery member inserted into the sample so as to recover the gas hydrate contained in the sample to the outside.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 8, 2017
    Assignee: Korea Gas Corporation
    Inventors: Seung Hee An, Young Soo Lee, Young Mi Jang, Young Ho Yang