Abstract: A method for fabricating a nonvolatile memory device includes forming a substrate structure having a tunnel dielectric layer and a floating-gate conductive layer formed over an active region defined by a first isolation layer forming a first inter-gate dielectric layer and a first control-gate conductive layer over the substrate structure, forming a trench by etching the first control-gate conductive layer, the first inter-gate dielectric layer, the floating-gate conductive layer, the tunnel dielectric layer, and the active region to a given depth, forming a second isolation layer to fill the trench; and forming a second control-gate conductive layer over the resultant structure having the second isolation layer formed therein.

Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.

Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.

Abstract: A method of manufacturing a semiconductor device for minimizing stress applied to a gate oxide layer or a tunnel oxide layer includes the steps of providing a semiconductor substrate in which a semiconductor device including a word line is formed, forming a capping layer including a first insulating layer having a compressive characteristic and a second insulating layer having a tensile characteristic on an entire surface of the substrate including the word line, and forming an interlayer insulating layer on the capping layer. In another aspect, the method also includes the steps of providing a semiconductor substrate in which a semiconductor device including a word line is formed, forming a capping layer on the entire surface including the word line by alternately forming a first insulating layer of a PECVD method and a second insulating layer of a LPCVD method, and forming an interlayer insulating layer on the capping layer.

Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.

Abstract: Provided is a method of manufacturing a capacitor in a semiconductor device, comprising the steps of: forming a first metal film of noble series for the bottom electrode; forming a ferroelectric film on the first metal film; conducting a first thermal process on the resultant structure where the ferroelectric film is formed; conducting an ion implantation process on the resultant structure passing through the first thermal process; conducting a second thermal process on the resultant structure passing through the ion implantation process; forming a second metal layer of noble series for the top electrode on the ferroelectric film in the resultant structure passing through the first thermal process; and conducting a third thermal process on the resultant structure.

Abstract: A flash memory device and a method of manufacturing the same, wherein a silicon layer having a micro grain is formed between a tunnel oxide layer and a floating gate using a hemi-spherical grain (HSG) method, thereby preventing the dopant of the floating gate from being diffused into the tunnel oxide layer. According to one embodiment, the flash memory device includes isolation structures formed in predetermined regions of a semiconductor substrate, for defining an active region and a field region, a tunnel oxide layer formed on the semiconductor substrate of the active region, and a floating gate formed in a predetermined region on the active region to overlap with a part of the isolation structure, an underlying given portion and the remaining portions of the floating gate having different grain sizes.

Abstract: Disclosed herein is a method of forming an element isolation film of a semiconductor device. An aluminum oxide film of a high wet etch rate is used as a pad oxide film, a trench is formed, and top and bottom edges of the trench is made rounded while removing some of the aluminum oxide film by a cleaning process. It is thus possible to make the top and bottom edges of the trench rounded without using polymer. It is also possible to minimize generation of a moat due to a step between a field region and an active region in a cleaning process before a gate oxide film is formed.

Abstract: Provided is a method of manufacturing a capacitor in a semiconductor device, comprising the steps of: forming a first metal film of noble series for the bottom electrode; forming a ferroelectric film on the first metal film; conducting a first thermal process on the resultant structure where the ferroelectric film is formed; conducting an ion implantation process on the resultant structure passing through the first thermal process; conducting a second thermal process on the resultant structure passing through the ion implantation process; forming a second metal layer of noble series for the top electrode on the ferroelectric film in the resultant structure passing through the first thermal process; and conducting a third thermal process on the resultant structure.

Abstract: The present invention relates to a method of forming an isolation film of a semiconductor device.

Abstract: A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.

Abstract: A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.