Abstract: A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6F2 saddle fin gate structure transistor, so that the size of a channel region increases. In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: defining an active region by forming a device isolation film over a semiconductor substrate; forming a first recess extending to a first level in the active region; forming a sacrificial film at a lower portion of the first recess; forming a fin structure over the sacrificial film; separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; and forming a gate to enclose the fin structure.

Abstract: An electronic device includes a device isolation film formed to define an active region in a substrate, a first gate buried to traverse the active region and the device isolation film in a first direction, and a second gate coupled to the first gate buried in the device isolation film, and extended in a second direction.

Abstract: The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.

Abstract: A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6F2 saddle fin gate structure transistor, so that the size of a channel region increases. In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: defining an active region by forming a device isolation film over a semiconductor substrate; forming a first recess extending to a first level in the active region; forming a sacrificial film at a lower portion of the first recess; forming a fin structure over the sacrificial film; separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; and forming a gate to enclose the fin structure.

Abstract: A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a gate disposed over a semiconductor substrate; a first spacer disposed over sidewalls of the gate; an insulating layer pattern disposed over sidewalls of the first spacer; and a second spacer disposed over the first spacer and the insulating pattern.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: A method for forming a semiconductor device includes: etching a hard mask layer and a conductive layer formed on a semiconductor substrate, a lower structure being formed on the semiconductor substrate; forming a sacrificial insulating layer at upper parts of the etched hard mask layer and the etched conductive layer of a peripheral circuit region; forming an isolation insulating layer at an upper part of an isolation insulating layer of a cell region; forming spacers at sidewalls of the etched hard mask layer, the etched conductive layer, and the isolation insulating layer of the cell region, respectively; forming storage electrode contact plugs at both sides of each of the spacers, respectively; and removing the sacrificial insulating layer to expose the semiconductor substrate of the peripheral circuit region, and etching the lower structure to expose the semiconductor substrate of the peripheral circuit region.

Abstract: A technology is capable of improving a process margin in forming a bit line and reducing bit line resistance to improve characteristic of the semiconductor device by forming a cell bit line in a double layer structure are provided. The semiconductor device includes a buried gate buried within a cell region of a semiconductor substrate, a first bit line formed over the semiconductor substrate, a second bit line formed over the first bit line and coupled to the first bit line. The first bit line is formed in the same layer as a peripheral gate of a peripheral circuit region and the second bit line is formed in the same layer as a metal line of the peripheral circuit region.

Abstract: The present invention relates to a decompression module using a gas stream and a vacuum apparatus for manufacturing a semiconductor device, in which the venturi effect due to a carrier gas stream is used to decompress an exhaust-side pressure of a vacuum pump without requiring an additional power, thereby being capable of appropriately reducing the load of the vacuum pump and the power consumption.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a gate disposed over a semiconductor substrate; a first spacer disposed over sidewalls of the gate; an insulating layer pattern disposed over sidewalls of the first spacer; and a second spacer disposed over the first spacer and the insulating pattern.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.

Abstract: A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.

Abstract: A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.

Abstract: The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove.

Abstract: A method for forming a semiconductor device includes: etching a hard mask layer and a conductive layer formed on a semiconductor substrate, a lower structure being formed on the semiconductor substrate; forming a sacrificial insulating layer at upper parts of the etched hard mask layer and the etched conductive layer of a peripheral circuit region; forming an isolation insulating layer at an upper part of an isolation insulating layer of a cell region; forming spacers at sidewalls of the etched hard mask layer, the etched conductive layer, and the isolation insulating layer of the cell region, respectively; forming storage electrode contact plugs at both sides of each of the spacers, respectively; and removing the sacrificial insulating layer to expose the semiconductor substrate of the peripheral circuit region, and etching the lower structure to expose the semiconductor substrate of the peripheral circuit region.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove.

Abstract: The sterilizing vacuum cleaner for bed clothes includes a housing including an ultraviolet (UV) irradiating space depressed into a bottom surface thereof, a suction port formed in the UV irradiating space, a discharge port formed in a side surface thereof, an air passage for connecting the suction port and the discharge port, and a sticking prevention passage depressed into the bottom extending to the side surface to prevent an object to be sterilized from adhering to the bottom surface. A first UV light emitter is installed in the housing to irradiate ultraviolet rays to the UV irradiating space of the housing.