Abstract: A apparatus for allocating physical resources at high speed includes: a storage unit storing correspondence relationships between virtual resource blocks and physical resource blocks according to external variables and internal variables; an internal variable calculation unit receiving the external variables for allocating physical resource blocks and calculating internal variables determined by the received external variables; and a searching unit referring to the storage unit by using the received external variables and allocating physical resources corresponding to the virtual resource blocks.

Abstract: Provided is a cell search method in a wireless communication system. According to the cell search method, when detecting SSS in order to search a cell group ID in 3GPP LTE communication, it is possible to reduce the computational complexity for SSS detection by selecting the sequence group of which cross-correlation between initially grouped SSS sequences is a predetermined value or more, computing cross-correlation with the sequences in the selected sequence group, and extracting a cell group ID through detection of the SSS sequence having the highest cross-correlation.

Abstract: There is provided a scrambling apparatus and a method of operating the same. A scrambling apparatus according to an aspect of the invention may include: a memory unit storing and providing a plurality of previously generated scrambling initial state codes; and a scrambling unit reading at least one of the plurality of scrambling initial state codes stored in the memory unit to generate a scrambling code in order to scramble an input signal, so that scrambling speed can be significantly increased.

Abstract: There is provided a signal detecting method using constellation set grouping in a spatial multiplexing multiple input multiple output system. The signal detecting method includes dividing a set of candidate symbols, a constellation set into a plurality of subsets by grouping the constellation set; dividing a tree search process of a QR-decomposition with M-algorithm (QRDM) algorithm into a plurality of partial detection phases; and performing the plurality of divided partial detection phases in parallel or iteratively.

Abstract: Provided are a method and apparatus for efficiently transferring a massive amount of multimedia data between two processors. The apparatus includes a first local switch, which connects a virtual page of a first processor element to a shared memory page, a second local switch, which connects a virtual page of a second processor element to the shared memory page, a shared page switch, which connects a predetermined shared memory page of a shared physical memory to the first or second local switch, and a switch manager, which remaps a certain shared memory page of the shared physical memory that stores data of a task performed by the first processor element to the virtual page of the second processor element. Accordingly, since memory remapping is used, the massive amount of multimedia data can be transmitted by changing a method of mapping a memory, unlike a case when multimedia data is transmitted by using a memory bus.

Abstract: Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly “1” when performing the FHT, and changes the input order of input data to a reverse order of bits when performing the FFT. In addition, the apparatus, which can process a plurality of input data sets simultaneously, classifies the received signals into multi-path signals and multi-antenna signals, thus processing the multi-path signals separately from the multi-antenna signals, or directly processes multi-antenna signals.

Abstract: A wireless modem is mounted to a terminal for wireless communication, and specifically controls an internal drive clock to reduce power consumption in an active mode. The wireless modem includes: a wireless core module for transmitting and receiving a radio signal; a modulator for converting data to be transmitted into a wireless transmission signal and transmitting the converted signal to the wireless core module; a demodulator for converting the signal received from the wireless core module into reception data; a synchronizer for synchronizing the signal received from the wireless core module; and a clock controller for generating a drive clock of each of the modulator, the demodulator, and the synchronizer. A low power clock controller is divided into six main functional blocks of a synchronizer, an analog controller, a modulator, a channel decoder, a demodulator, and a channel encoder, and has a feature that a clock is input only when a main functional block operates.

Abstract: Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly “1” when performing the FHT, and changes the input order of input data to a reverse order of bits when performing the FFT. In addition, the apparatus, which can process a plurality of input data sets simultaneously, classifies the received signals into multi-path signals and multi-antenna signals, thus processing the multi-path signals separately from the multi-antenna signals, or directly processes multi-antenna signals.