Abstract: A pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. Plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. Plural second switches are configured to output the plural data entries stored in the plural second inverter latches.

Abstract: A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

Abstract: A memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. The merge group comprises at least two memory banks in a same plane group.

Abstract: A column address generation circuit including: a command set conversion section configured to generate column address information on the basis of sector information included in a first command set synchronized with a first clock signal, and to output a second command set from the first command set by replacing information on column address cycles of the first clock signal with the column address information in response to a conversion signal; and a column address output section configured to output a column address on the basis of the second command set.

Abstract: A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Abstract: The present technology relates to a semiconductor device. According to the present technology, a memory device having a reduced size may include a plurality of memory cells connected to a selected word line, a plurality of page buffers configured to store at least one second logical page data except for first logical page data in a plurality of first program loops performed on the plurality of memory cells, and store the first logical page data after the plurality of first program loops are performed, and a control logic configured to control the plurality of first program loops based on the at least one second logical page data, determine first memory cells programmed to one program state based on the first logical page data, and control a plurality of second program loops performed on second memory cells.

Abstract: A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.