Patents by Inventor Young Soo Ahn

Young Soo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9096946
    Abstract: A dual crucible for silicon melting and a manufacturing apparatus of a silicon thin film including the same are disclosed. The dual crucible for the silicon melting includes a graphite crucible formed in a container shape with an open top and a bottom having an outlet part formed therein to exhaust silicon melt, the graphite crucible comprising a slope part configured to connect the outlet part and an inner wall with each other, with a predetermined slope with respect to a top surface of the outlet part, and a quartz crucible insertedly coupled to the graphite crucible, with being formed in a corresponding shape to the graphite crucible, the quartz crucible having a silicon base material charged therein.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: August 4, 2015
    Assignee: Korea Institute of Energy Research
    Inventors: Jin Seok Lee, Bo Yun Jang, Young Soo Ahn
  • Publication number: 20150214240
    Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Young-Soo AHN, Jeong-Seob OH
  • Patent number: 9087688
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 21, 2015
    Assignee: SK HYNIX INC.
    Inventor: Young Soo Ahn
  • Patent number: 9076958
    Abstract: A resistive memory device includes word lines stacked on top of one another, at least one first selection line formed over the word lines, a first channel layer passing through the word lines and the first selection line, a first phase change material layer formed in the first channel layer and overlapping the word lines, and a first insulating layer formed in the first channel layer and overlapping the first selection line.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Soo Ahn
  • Patent number: 9040010
    Abstract: The present disclosure provides an apparatus for manufacturing a single crystal silicon ingot having a dual crucible for silicon melting which can be reused due to a dual crucible structure. The apparatus includes a dual crucible for silicon melting, into which raw silicon is charged, a crucible heater heating the dual crucible to melt the raw silicon into molten silicon, a crucible drive unit controlling rotation and elevation of the dual crucible, and a pull-up drive unit disposed above the dual crucible and pulling up a seed crystal dipped in the molten silicon to produce a silicon ingot. The dual crucible has a container shape open at an upper side thereof, and includes a graphite crucible having an inclined surface connecting an inner bottom and an inner wall, and a quartz crucible inserted into the graphite crucible and receiving the raw silicon charged into the dual crucible.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: May 26, 2015
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jin-Seok Lee, Bo-Yun Jang, Young-Soo Ahn
  • Patent number: 9024372
    Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young-Soo Ahn, Jeong-Seob Oh
  • Patent number: 8997524
    Abstract: Methods and apparatus for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit which is placed on a first electron beam-irradiating region corresponding to the first electron gun and to which powdery raw silicon is fed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun. The unidirectional solidification unit is provided therein with a start block driven in a downward direction to transfer molten silicon in the downward direction and is formed at a lower side thereof with a cooling channel. The start block includes a dummy bar having a silicon button joined to an upper portion of the dummy bar.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: April 7, 2015
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Jin Seok Lee, Joon Soo Kim, Young Soo Ahn
  • Patent number: 9001863
    Abstract: A graphite crucible for electromagnetic induction-based silicon melting and an apparatus for silicon melting/refining using the same, which performs a melting operation by a combination of indirect melting and direct melting. The crucible is formed of a graphite material and includes a cylindrical body having an open upper part through which a silicon raw material is charged into the crucible, and an outer wall surround by an induction coil, wherein a plurality of first slits are vertically formed through the outer wall and an inner wall of the crucible, and a plurality of second slits are vertically formed from an edge of the disc-shaped bottom of the crucible toward a center of the bottom.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: April 7, 2015
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Young Soo Ahn, Joon Soo Kim, Sang Hyun Park, Dong Kook Kim, Gwon Jong Yu
  • Publication number: 20150090406
    Abstract: Provided is a method of disassembling a photovoltaic module. The method includes: applying heat to the photovoltaic module in an oxidizing atmosphere; removing an insulating protective layer wrapping a photovoltaic cell of the photovoltaic module; and obtaining the photovoltaic cell of the photovoltaic module.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 2, 2015
    Inventors: Jin Seok LEE, Young Soo AHN, Bo Yun JANG, Joon Soo KIM, Gi Hwan KANG
  • Patent number: 8968470
    Abstract: Disclosed herein are a graphite crucible for electromagnetic induction-based silicon melting and an apparatus for silicon melting/refining using the same, which performs a melting operation by a combination of indirect melting and direct melting. The crucible is formed of a graphite material and includes a cylindrical body having an open upper part through which a silicon raw material is charged into the crucible, and an outer wall surrounded by an induction coil, wherein a plurality of slits are vertically formed through the outer wall and an inner wall of the crucible such that an electromagnetic force created by an electric current flowing in the induction coil acts toward an inner center of the crucible to prevent a silicon melt from contacting the inner wall of the crucible.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: March 3, 2015
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Young Soo Ahn, Joon Soo Kim, Sang Hyun Park, Dong Kook Kim, Gwon Jong Yu
  • Patent number: 8921182
    Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Wook Jung, Yun-Kyoung Lee, Young-Soo Ahn, Tae-Hwa Lee
  • Publication number: 20140349455
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 27, 2014
    Inventor: Young Soo AHN
  • Patent number: 8894893
    Abstract: A method of preparing transparent or nontransparent silica aerogel granules. The method includes forming a granular wet gel by spraying a silica sol into alcohol, the silica sol being prepared by mixing a water glass solution or an opacifier-containing water glass solution with an inorganic acid solution, forming a granular alcohol gel through gelation aging and solvent substitution of the granular wet gel in alcohol, hydrophobically modifying the surface of the granular alcohol gel using an organic silane compound, and drying the surface modified gel at ambient pressure or in a vacuum. The method may prepare silica aerogel granules in a short period of time through heat treatment at a relatively low temperature and at ambient pressure or in a vacuum, thereby ensuring excellent economic feasibility, continuity and reliability, suited for mass production.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 25, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Young-Soo Ahn, Jeong-gu Yeo, Churl-Hee Cho
  • Publication number: 20140342519
    Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventors: Yoo Hyun NOH, Jong Moo CHOI, Young Soo AHN
  • Patent number: 8871140
    Abstract: Disclosed herein is a method of manufacturing inorganic hollow yarns, such as cermets, oxide-non oxide composites, poorly sinterable non-oxides, and the like, at low costs. The method includes preparing a composition comprising a self-propagating high temperature reactant, a polymer and a dispersant, wet-spinning the composition through a spinneret to form wet-spun yarns, washing and drying the wet-spun yarns to form polymer-self propagating high temperature reactant hollow yarns, and heat-treating the polymer-self propagating high temperature reactant hollow yarns to remove a polymeric component from the polymer-self propagating high temperature reactant hollow yarns while inducing self-propagating high temperature reaction of the self-propagating high temperature reactant to form inorganic hollow yarns. The composition comprises 45˜60 wt % of the self-propagating high temperature reactant, 6˜17 wt % of the polymer, 0.1˜4 wt % of the dispersant, and the balance of an organic solvent.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Churl-Hee Cho, Do-Kyung Kim, Jeong-Gu Yeo, Young-Soo Ahn, Dong-Kook Kim, Hong-Soo Kim
  • Patent number: 8829599
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Young Soo Ahn
  • Patent number: 8794035
    Abstract: Apparatus and method for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber maintaining a vacuum atmosphere; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit placed on a first electron beam-irradiating region corresponding to the first electron gun and in which powdery raw silicon is placed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun and connected to the silicon melting unit via a runner. The unidirectional solidification unit is formed at a lower part thereof with a cooling channel and is provided therein with a start block driven in a downward direction.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Jin Seok Lee, Joon Soo Kim, Young Soo Ahn
  • Publication number: 20140160837
    Abstract: A resistive memory device Includes word lines stacked on top of one another, at least one first selection line formed over the word lines, a first channel layer passing through the word lines and the first selection line, a first phase change material layer formed in the first channel layer and overlapping the word lines, and a first insulating layer formed in the first channel layer and overlapping the first selection line.
    Type: Application
    Filed: March 16, 2013
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventor: Young Soo AHN
  • Patent number: 8735641
    Abstract: Disclosed is a method for selective dealkylation of alkyl-substituted C9+ aromatic compounds using a bimodal porous dealkylation catalyst at a low temperature. The catalyst has a bimodal porous structure including both mesopores and micropores. The catalyst includes a crystalline aluminosilicate and a metal. The catalyst is highly active at a low temperature. According to the method, C9+ aromatic compounds substituted with at least one C2+ alkyl group as by-products formed by xylene production can be selectively dealkylated and converted to BTX, etc. on a large scale within a short time. In addition, the method is an environmentally friendly process entailing reduced waste treatment cost when compared to conventional mesitylene production methods. Therefore, high value-added mesitylene can be separated from low value-added C9+ aromatic compounds at lower cost compared to conventional methods.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 27, 2014
    Assignees: S-Oil Corporation, Inha-Industry Partnership Institute
    Inventors: Sung Hyeon Baeck, Geon Joong Kim, Dong-Kyun Noh, Tae Young Jang, Tae-Yun Kim, Young Soo Ahn, Chan-ju Song, Sang-Cheol Paik
  • Patent number: 8687425
    Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Young-Soo Ahn, Jong-Moo Choi, Yoo-Hyun Noh