Patents by Inventor Young-Sub You

Young-Sub You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050277252
    Abstract: Methods of forming a gate structure of a non-volatile memory device include forming a gate pattern having a control gate on a semiconductor substrate. An oxidation-preventing layer is formed on the control gate in a process chamber while maintaining a substantially oxygen free atmosphere in the process chamber. An oxide spacer is formed on a sidewall of the gate pattern with the oxidation-preventing layer thereon in the process chamber. Forming an oxidation-preventing layer may include exposing the gate pattern to a first gas in the process chamber and forming an oxide spacer may include exposing the gate pattern to a second gas including oxygen in the process chamber.
    Type: Application
    Filed: June 3, 2005
    Publication date: December 15, 2005
    Inventors: Young-Sub You, Ki-Su Na, Hun-Hyeoung Leam, Woong Lee
  • Publication number: 20050266640
    Abstract: A method of forming a dielectric layer having a reduced thickness according to embodiments of the invention includes forming a lower oxide layer on a substrate, and forming a nitride layer on the lower oxide layer. Then, a preliminary oxide layer is formed on the nitride layer. A radical oxidation process using oxygen radicals is performed on the preliminary oxide layer to form an upper oxide layer on the nitride layer. The dielectric layer includes an ONO composite layer consisting of the lower oxide layer, the nitride layer, and the upper oxide layer. Due to the decreased thickness of the dielectric layer, the dielectric layer has an improved capacitance and an increased coupling coefficient.
    Type: Application
    Filed: May 6, 2005
    Publication date: December 1, 2005
    Inventors: Young-Sub You, Woong Lee, Hun-Hyeoung Leam, Hyeon-Deok Lee, Ki-Su Na, Yong-Woo Hyung, Jai-Dong Lee
  • Publication number: 20050153513
    Abstract: A method of forming a dielectric layer for a non-volatile memory cell is disclosed. According to the method, a dielectric layer is formed by successively forming a lower oxide layer, a nitride layer and an upper oxide layer on a semiconductor substrate. The lower and upper oxide layers are formed using a radical oxidation process. A method of forming a non-volatile memory cell having the dielectric layer is also disclosed.
    Type: Application
    Filed: November 22, 2004
    Publication date: July 14, 2005
    Inventors: Woong Lee, Young-Sub You, Hun-Hyeoung Leam, Ki-Su Na, Man-Sug Kang, Jung-Hwan Kim, Jai-Dong Lee
  • Publication number: 20050153518
    Abstract: A method for forming a capacitor comprises forming a supporting insulating film, an etching stopper film made of alumina series or hafnium oxide series, and a mold insulating film on a surface of a semiconductor substrate having a first structure including conductive plugs surrounded by a first insulating film, patterning the mold insulating film, the etching stopper film and the supporting insulating film to form openings that expose the conductive plugs, forming a storage node conductive film electrically connected to the conductive plugs on the surface of the semiconductor substrate having the openings formed therein and concurrently annealing the etching stopper film, separating the storage node conductive film to form a plurality of storage nodes, exposing at least a part of an outer surface of the storage node by selectively etching remaining mold insulating film, which is exposed by the separated storage node conductive film, until the etching stopper film is exposed, and forming a plurality of plate n
    Type: Application
    Filed: December 15, 2004
    Publication date: July 14, 2005
    Inventors: Young-Sub You, Jung-Hwan Oh, Ki-Su Na, Seok-Woo Nam, Hun-Hyeoung Leam
  • Patent number: 6913979
    Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hyeon-Deok Lee, Tae-Soo Park, Heon-Heoung Leam, Bong-Hyun Kim, Yong-Woo Hyung
  • Publication number: 20040229432
    Abstract: Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530° C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580° C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.
    Type: Application
    Filed: October 31, 2003
    Publication date: November 18, 2004
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Sang-Hoon Lee
  • Publication number: 20040224531
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 11, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20040219772
    Abstract: An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 4, 2004
    Inventors: Young-Sub You, Jae-Woong Kim
  • Patent number: 6797561
    Abstract: A method of fabricating a capacitor of a semiconductor device, includes forming a lower electrode on a semiconductor substrate, sequentially forming an aluminum oxide layer and a titanium oxide layer on the lower electrode, and forming an upper electrode on the titanium oxide layer, wherein the upper electrode crosses over the lower electrode. The titanium oxide layer is formed to have a thickness in a range of from about 2 Å to about 50 Å, and the upper electrode is formed at a temperature in a range of from about 150° C. to about 630° C. The temperature at which the upper electrode is formed is decreased as the thickness of the titanium oxide layer is increased to produce a capacitor of a semiconductor device having a minimized leakage current characteristic.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: September 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Hyun Ko, Young Sub You, Jai Dong Lee, Ki Hyun Hwang
  • Publication number: 20040061169
    Abstract: A non-volatile memory device includes gate stack structures formed on a semiconductor substrate to be separated by a first space in a first area and by a second wider space in a second area adjacent to the first area. First gate spacers of a low dielectric constant insulating material are formed on the sidewalls of the gate stack structures. Second gate spacers made of an insulating material having good step coverage are formed on the first gate spacers to fill the first space. This dual spacer structure comprising the first gate spacer and the second gate spacer prevents the creation of void between gates. Thus, it can prevent an active region from being opened in a subsequent etching process and preclude the formation of a silicide layer on the active region. Thus, the device characteristics can be substantially improved.
    Type: Application
    Filed: July 29, 2003
    Publication date: April 1, 2004
    Inventors: Heon-Heoung Leam, Yong-Woo Hyung, Young-Sub You, Woo-Sung Lee
  • Publication number: 20040058556
    Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.
    Type: Application
    Filed: April 30, 2003
    Publication date: March 25, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hyeon-Deok Lee, Tae-Soo Park, Heon-Heoung Leam, Bong-Hyun Kim, Yong-Woo Hyung
  • Patent number: 6706613
    Abstract: A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: March 16, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Lim, Sang-Hoon Lee, Woo-Sung Lee
  • Publication number: 20040029354
    Abstract: A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.
    Type: Application
    Filed: February 6, 2003
    Publication date: February 12, 2004
    Inventors: Young-Sub You, Hun-Hyeoung Lim, Sang-Hoon Lee, Woo-Sung Lee
  • Publication number: 20030190782
    Abstract: A method of fabricating a capacitor of a semiconductor device, includes forming a lower electrode on a semiconductor substrate, sequentially forming an aluminum oxide layer and a titanium oxide layer on the lower electrode, and forming an upper electrode on the titanium oxide layer, wherein the upper electrode crosses over the lower electrode. The titanium oxide layer is formed to have a thickness in a range of from about 2 Å to about 50 Å, and the upper electrode is formed at a temperature in a range of from about 150° C. to about 630° C. The temperature at which the upper electrode is formed is decreased as the thickness of the titanium oxide layer is increased to produce a capacitor of a semiconductor device having a minimized leakage current characteristic.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 9, 2003
    Inventors: Chang Hyun Ko, Young Sub You, Jai Dong Lee, Ki Hyun Hwang