Patents by Inventor Young-Hoon Ro
Young-Hoon Ro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9502341Abstract: Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.Type: GrantFiled: March 5, 2015Date of Patent: November 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jik-Ho Song, Ga-Young Kim, Woo-Jae Kim, Young-Hoon Ro
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Publication number: 20160049379Abstract: Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.Type: ApplicationFiled: March 5, 2015Publication date: February 18, 2016Inventors: Jik-Ho SONG, Ga-Young KIM, Woo-Jae KIM, Young-Hoon RO
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Patent number: 8446018Abstract: A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads.Type: GrantFiled: March 7, 2011Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Jae Kim, Young-Hoon Ro, Sung-Woo Park
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Patent number: 8274144Abstract: A first semiconductor package includes a first substrate, a first semiconductor chip attached to the first substrate, an encapsulant which covers the first semiconductor chip, and conductive elastic members which are embedded in the encapsulant but with parts thereof exposed. A package on package (POP) includes the first semiconductor package and a second semiconductor package stacked in the first semiconductor package. The second semiconductor package includes a second substrate and a second semiconductor chip attached to the second substrate. The exposed parts of the elastic members are electrically connected to the second substrate. The encapsulant of the first package is formed by a molding process while the conductive elastic members are compressed within their elastic limit by the mold.Type: GrantFiled: May 24, 2011Date of Patent: September 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Hoon Ro
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Publication number: 20120049348Abstract: A first semiconductor package includes a first substrate, a first semiconductor chip attached to the first substrate, an encapsulant which covers the first semiconductor chip, and conductive elastic members which are embedded in the encapsulant but with parts thereof exposed. A package on package (POP) includes the first semiconductor package and a second semiconductor package stacked in the first semiconductor package. The second semiconductor package includes a second substrate and a second semiconductor chip attached to the second substrate. The exposed parts of the elastic members are electrically connected to the second substrate. The encapsulant of the first package is formed by a molding process while the conductive elastic members are compressed within their elastic limit by the mold.Type: ApplicationFiled: May 24, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Young-Hoon Ro
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Publication number: 20110215471Abstract: A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads.Type: ApplicationFiled: March 7, 2011Publication date: September 8, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Jae Kim, Young-Hoon Ro, Sung-Woo Park
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Patent number: 7855895Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.Type: GrantFiled: October 28, 2009Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Han Kim, Young-Hoon Ro
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Publication number: 20100038438Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.Type: ApplicationFiled: October 28, 2009Publication date: February 18, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Han Kim, Young-Hoon Ro
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Publication number: 20090315130Abstract: A solid-state imaging apparatus and method for manufacturing the imaging apparatus. A solid-state imaging apparatus with reduced thickness and/or mounting area by forming an aperture in a board and placing a solid-state semiconductor imaging chip, an image processing semiconductor chip, and/or a combination imaging/processing chip within the aperture.Type: ApplicationFiled: August 11, 2004Publication date: December 24, 2009Inventors: Young-Hoon Ro, Young-Shin Kwon, Seung-Kon Mok
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Patent number: 7630209Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.Type: GrantFiled: July 14, 2006Date of Patent: December 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Han Kim, Young-Hoon Ro
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Patent number: 7579583Abstract: A size reduced solid-state imaging apparatus may be provided. The solid-state imaging apparatus may include a wiring substrate having a body having a cavity on an area which a semiconductor chip may be mounted, a lead that may project inward into the cavity from the internal side of the body, and/or a tie bar.Type: GrantFiled: November 1, 2004Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Kon Mok, Young-Hoon Ro
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Patent number: 7405760Abstract: An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.Type: GrantFiled: January 21, 2003Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kyo Cho, Sa Yoon Kang, Young Hoon Ro, Young Shin Kwon
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Publication number: 20070013396Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.Type: ApplicationFiled: July 14, 2006Publication date: January 18, 2007Inventors: Dong-Han KIM, Young-Hoon RO
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Publication number: 20070015338Abstract: A substrate, a smart card module having the substrate and methods for fabricating the same are provided. A substrate having metal patterns formed on both sides and applicable to both wire bonding and flip chip bonding, a smart card module having the same and methods of fabricating the same are also provided. The substrate may include an insulating layer, an upper metal pattern, a bottom metal pattern, a first plating layer, a second plating layer and a substrate. The insulating layer may have a plurality of via holes. The upper metal pattern may be formed on the insulating layer and side surfaces of the plurality of via holes. The bottom metal pattern may be formed on the bottom of the insulating layer and electrically connected to the upper metal pattern. The first plating layer may be formed on the upper metal pattern and the upper surface of the bottom metal pattern. The second plating layer may be formed on the bottom of the bottom metal pattern.Type: ApplicationFiled: July 17, 2006Publication date: January 18, 2007Inventors: Seok-Won Lee, Kyoung-Sei Choi, Dong-Han Kim, Young-Hoon Ro
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Publication number: 20050116142Abstract: A size reduced solid-state imaging apparatus may be provided. The solid-state imaging apparatus may include a wiring substrate having a body having a cavity on an area which a semiconductor chip may be mounted, a lead that may project inward into the cavity from the internal side of the body, and/or a tie bar.Type: ApplicationFiled: November 1, 2004Publication date: June 2, 2005Inventors: Seung-Kon Mok, Young-Hoon Ro
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Patent number: 6891259Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.Type: GrantFiled: August 21, 2003Date of Patent: May 10, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Hyeok Im, Young-Hoon Ro
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Publication number: 20040036183Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.Type: ApplicationFiled: August 21, 2003Publication date: February 26, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Yun-Hyeok Im, Young-Hoon Ro
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Publication number: 20030234886Abstract: An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.Type: ApplicationFiled: January 21, 2003Publication date: December 25, 2003Inventors: Min Kyo Cho, Sa Yoon Kang, Young Hoon Ro, Young Shin Kwon
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Patent number: 6608380Abstract: A semiconductor chip package comprising a chip with a lid having venting holes hermetically sealed with screws and a manufacturing method thereof are provided. The semiconductor chip package of the present invention comprises a chip such as a central processing unit (CPU) chip generating a large amount of heat; a substrate having upper and lower surfaces, the chip attached to the upper surface of the substrate; external connection terminals extending from the lower surface of the substrate and electrically connected to the chip; a lid attached to the upper surface of the substrate. The lid has a cavity for receiving the chip on a lower surface and venting holes penetrating the lid. The package includes sealing screws for hermetically sealing the venting holes. With the present invention, the venting holes formed through the lid are hermetically sealed without creating any voids or cracks in the sealant as in the prior art.Type: GrantFiled: October 9, 2001Date of Patent: August 19, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoon Ro, Jung-Hwan Chun, Heung-Kyu Kwon
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Publication number: 20030085475Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.Type: ApplicationFiled: October 10, 2002Publication date: May 8, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Yun-Hyeok Im, Young-Hoon Ro