Abstract: Field oxide regions are formed in a dry oxygen environment containing controlled amounts of HCl at elevated temperatures to reduce edge defects of narrow source/drain regions.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode as a mask, and heating to form thin, self-aligned buried oxide regions extending from a field oxide region under source/drain regions self-aligned with the side surfaces of the gate electrode. In other embodiments, the thin buried oxide layer extends from a point in close proximity to the field oxide region and/or partially under the gate electrode.

Abstract: A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.

Abstract: A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region.

Abstract: A semiconductor structure includes isolation regions fabricated by a hybrid local oxidation of silicon (LOCOS) technique and a trench isolation technique. Wide and narrow gaps or spacings are etched in a multilayer silicon structure. The wide gaps are covered by a photoresist, and the narrow gaps are further etched to form deep trenches. The wide spacing and deep trenches are filled with an insulative material such as TEOS. The TEOS is etched and the structure is heated to cause local oxidation of silicon in the deep trench and wide spacing. The hybrid fabrication technique is particularly useful in complementary metal oxide semiconductor (CMOS) technology where wide isolation units are utilized to separate transistors sharing the same gate and trenches are utilized to isolate transistors sharing the same well.

Abstract: A method of defining a local oxidation of silicon (LOCOS) field isolation process after a poly gate is deposited. A gate oxide is grown on a silicon substrate, and then poly or amorphous silicon is deposited. A thin layer of PECVD or LPCVD oxide is deposited on the poly, and LPCVD nitride is then deposited as a hard mask. A device active area is defined by photoresist mask and plasma etch. The layers may either be etched down to the silicon surface, or the silicon surface may be further etched to create a recessed silicon region.An oxide layer is grown on the exposed sidewalls of the poly, and another layer of nitride is deposited. The nitride is etched to form a nitride spacer, and a field oxide is grown. A field isolation implant is formed, followed by stripping the nitride space. The oxide layer is removed, reexposing the poly. Another layer of poly and WSi film is deposited, and gate and interconnects are defined by applying a gate mask and etch.

Abstract: A method of fabricating an FET or CMOS transistor that includes lightly doped drain ("LDD") regions which minimizes oxide loss while requiring a lesser number of masks. Consequently, manufacturing cost, cycle times and yield loss can be minimized.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract: A novel CMOS fabrication process that eliminates several masks of a conventional process by delaying application of a well mask to a semiconductor structure until after formation of isolation regions and gate structures. Providing for three separate implant steps and selectively implanting dopants through an exposure window of the well mask, through gate structures, and through the well mask allows formation of the well region, and source/drain regions in the well region, and in the region covered by the well mask. When LDD implants are desired, removal of a lateral spacer on the gate overlying the well region and subsequent LDD implant through the mask region introduces the LDD implant. Separate masks for source/drain regions and LDD regions are not required. In an alternate embodiment, the LDD implant is introduced prior to formation of lateral spacers on gate structures and application of the well mask, providing the LDD implant in both channels, and eliminating a requirement for lateral spacer removal.

Abstract: Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep imp