Patents by Inventor Yu Cai

Yu Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027519
    Abstract: A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device, using multiple read threshold entries and determines which are good read threshold entries based on results of the read operation. The controller selects a best read threshold entry among the multiple read threshold entries based on a result of the test read operation, partitions the read data set into a good data set decodable by the best read threshold entry and a bad data set undecodable by the best read threshold entry, and sets the bad data set as a new read data set.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 23, 2020
    Inventors: Fan ZHANG, Yu CAI, Chenrong XIONG, Xuanxuan LU
  • Patent number: 10535410
    Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Yu Cai, Fan Zhang, June Lee
  • Publication number: 20200004626
    Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: David J PIGNATELLI, Fan ZHANG, Yu CAI
  • Publication number: 20200004422
    Abstract: Embodiments of the present disclosure provide a method and device for storing data. The method comprises: generating a data block corresponding to data to be stored; aligning the data block to a boundary of a tracking unit of a predefined size for validating the data; and storing the aligned data block in at least one storage unit of a storage space, the at least one storage unit having an identical size. The method according to embodiments of the present disclosure can align the data block so as to minimize the waste of storage space and avoid the situation where the rest data cannot be validated due to disappearance of partial data.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Lu Lei, Chen Wang, Gary Jialei Wu, Ronnie Yu Cai, Ao Sun
  • Patent number: 10521299
    Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 31, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ronnie Yu Cai, Ao Sun, Gary Jialei Wu, Lu Lei, Chen Wang
  • Publication number: 20190385684
    Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Aman BHATIA, Chenrong XIONG, Fan ZHANG, Naveen KUMAR, Yu CAI
  • Publication number: 20190387557
    Abstract: A terminal communication method includes obtaining, by a communications device, start information and length information, where the start information is used to indicate a start location of a first time resource. The method further comprises determining the first time resource based on the start information and the length information, where the first time resource is used to indicate a transmit or receive time resource of a sidelink signal.
    Type: Application
    Filed: January 26, 2017
    Publication date: December 19, 2019
    Inventors: Yu Cai, Yongbo Zeng, Da Wang
  • Publication number: 20190386803
    Abstract: A resource selection method includes monitoring, by a first terminal, a first subframe, where a quantity of the first subframes is less than or equal to a quantity of second subframes; receiving, by the first terminal, indication information in the first subframe determining, by the first terminal, a first resource in the second subframe according to the indication information; and selecting, according to the first resource, a resource in the second subframe for the first terminal to send data. There may be one or more first subframes; the second subframe may be a candidate subframe, and there may be one or more candidate subframes. The indication information includes information that can indicate a resource reserved by a second terminal, that is, indication information that can indicate a resource excluded by the second terminal.
    Type: Application
    Filed: January 26, 2017
    Publication date: December 19, 2019
    Inventors: Yu Cai, Yongbo Zeng, Da Wang
  • Publication number: 20190377635
    Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 12, 2019
    Inventors: Chenrong XIONG, Aman BHATIA, Fan ZHANG, Naveen KUMAR, Xuanxuan LU, Yu CAI
  • Publication number: 20190379405
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 12, 2019
    Inventors: Kyoung Lae CHO, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Patent number: 10504972
    Abstract: An organic light emitting display panel and a method for manufacturing the same are provided. The organic light emitting display panel includes: an organic light emitting element array substrate; a thin film encapsulation layer covering the organic light emitting element array substrate and including at least one inorganic layer and at least one organic layer; a wettability adjustment layer disposed on an organic layer or inorganic layer of the thin film encapsulation layer and including a plurality of wettability adjustment pattern zones and a plurality of hollow zones, and touch electrodes made of metal. The touch electrodes are in a meshed shape and disposed in the hollow zones. A wetting angle between material of the touch electrodes and the wettability adjustment pattern zones is greater than a wetting angle between the material of the touch electrodes and the organic layer or the inorganic layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 10, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Yu Cai
  • Patent number: 10503327
    Abstract: An organic light-emitting display panel and fabrication method thereof are provided. The organic light-emitting display panel includes an organic light-emitting element array substrate, a thin film encapsulation layer covering the organic light-emitting element array substrate, and touch-control electrodes. The thin film encapsulation layer includes at least one inorganic layer and at least one organic layer. First groove structures are configured in at least one organic layer, and sidewalls of the first groove structures are arc-shaped. The touch-control electrodes are disposed in the first groove structures.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: December 10, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yu Cai, Xuening Liu, Heeyol Lee, Quanpeng Yu, Conghui Liu
  • Patent number: 10491243
    Abstract: Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements low-density parity-check (LDPC) decoding that uses bit flipping. In a decoding iteration, a feature map is generated for a bit of an LDPC codeword. The bit corresponds to a variable node. The feature map is input to a neural network that is trained to determine whether bits should be flipped based on corresponding feature maps. An output of the neural network is accessed. The output indicates that the bit should be flipped based on the feature map. The bit is flipped in the decoding iteration based on the output of the neural network.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 26, 2019
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Chenrong Xiong, Yu Cai, Fan Zhang
  • Publication number: 20190357154
    Abstract: In the embodiments of the present invention, a first-type terminal increases signal transmit power and/or a second-type terminal decreases signal transmit power, or when selecting a resource location for signal transmission, a terminal may exclude a resource location that is close in frequency domain to and located in a same time interval as a resource location reserved by another terminal of a different type, or resource locations used by different types of terminals to transmit signals are separated by a resource location occupied by a guard band, to reduce in-band emission interference.
    Type: Application
    Filed: September 30, 2016
    Publication date: November 21, 2019
    Inventors: Yongbo Zeng, Yu Cai, Jian Wang
  • Publication number: 20190357213
    Abstract: A resource indication method and a related device, where the method includes the obtaining system resource information of a second system, and sending indication information using a resource of a first system, where the indication information indicates the system resource information such that a device receiving the indication information determines the system resource information based on the indication information. Hence, an indication message indicating a system resource of the second system is sent using the resource of the first system. Therefore, a user equipment directly determine the system resource information of the second system based on the indication information, and efficiency of accessing the second system by the user equipment is improved.
    Type: Application
    Filed: August 12, 2016
    Publication date: November 21, 2019
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Yu CAI, Jian WANG, Yongbo ZENG, Da WANG
  • Publication number: 20190357304
    Abstract: A signal transmission method and a terminal, where a first terminal sets first information indicating a terminal type of the first terminal, and sends a signal including, the first information to a second terminal such that the second terminal identifies the terminal type of the first terminal based on the first information. The first information is set, and the signal including the first information is sent to the second terminal such that the second terminal identifies the terminal type of the first terminal based on the first information and processes the processed signal based on the terminal type of the first terminal to prevent, by distinguishing types of terminals, signal interference from being caused between different terminals.
    Type: Application
    Filed: August 12, 2016
    Publication date: November 21, 2019
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Yongbo ZENG, Yu CAI, Jian WANG
  • Patent number: 10484008
    Abstract: Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Abhiram Prabhakar, Aman Bhatia, Yu Cai, Naveen Kumar
  • Publication number: 20190340068
    Abstract: Encoders and decoders are provided for memory systems. An encoder scrambles data bits corresponding to a logical page, selected from among multiple logical pages, using a plurality of random sequences, to generate a plurality of scrambled sequences; selects, as an encoded sequence, a scrambled sequence among the plurality of scrambled sequences; and provides a memory device with the encoded sequence to store the encoded sequence in multiple level cells. The selected scrambled sequence has the lowest number of logical high values among the plurality of scrambled sequences.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 7, 2019
    Inventors: Aman BHATIA, Yu CAI, Naveen KUMAR, Xuanxuan LU, Chenrong XIONG, Fan ZHANG
  • Publication number: 20190340062
    Abstract: Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 7, 2019
    Inventors: Yu CAI, Chenrong XIONG, Fan ZHANG, Naveen KUMAR, Aman BHATIA, Xuanxuan LU
  • Publication number: 20190340069
    Abstract: Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 7, 2019
    Inventors: Naveen KUMAR, Aman BHATIA, Yu CAI, Fan ZHANG