Abstract: Embodiments of the present invention disclose a control information processing method and system, a first device, and a second device.

Abstract: A device-to-device (D2D) communication method and a D2D terminal device, where the method includes determining, by a first device, a time that the first device is out of coverage of a synchronization source after leaving the coverage of the synchronization source determining, by the first device, target timing based on the time, and performing, by the first device, D2D communication based on the target timing. Hence, the target timing can be selected more accurately for the first device.

Abstract: An electronic system and a control method thereof are provided. The electronic system includes a first device, a second device and a control device. The first device includes a first processor and a first control module, and the first control module is electrically connected to the first processor. The second device is detachably disposed on the first device. The second device includes a second processor and a second control module, and the second control module is electrically connected to the second processor. The control device is detachably connected to the second device, and the first device, the second device and the control device are coupled to each other.

Abstract: This application discloses a signal transmission method and a related device. The method may include: sending, by a first terminal, a first message to a network device, where the first message is used to indicate a transmission mode used by the first terminal to transmit a signal; receiving a second message sent by the network device, where the second message is used to indicate a resource used by the first terminal to transmit the signal; and transmitting the signal on the resource. According to the foregoing solution, a terminal may transmit a signal by using different transmission modes and resources.

Abstract: A power control method, a terminal, and a network device include, when any one of two terminals that perform direct communication determines a transmission power of the terminal, the terminal determines the transmission power based on at least one of a path loss between the two terminals, and a channel quality status of another terminal used as a receive end.

Abstract: A system includes memory cells arranged in blocks and a memory controller. The memory controller receives a read command to read a first block. The first block can be associated with a first read count and a first read threshold. The first read count is incremented when the first block is read, and when the first read count reaches the read threshold, a read reclaim test is performed. The first read count is set to zero after a power off or a read reclaim operation. When the first read count is zero, an adaptive read threshold is selected based on the number of bit errors. Further, in a read reclaim test, the number of bit errors is tested against an adaptive error threshold to determine whether a garbage collection operation is performed.

Abstract: This application provides a method that includes the step of receiving, by a first device in a first time domain position, first scheduling information. The first scheduling information includes first indication information sent by a network device, wherein the first indication information is used to indicate a first interval. The method further comprises sending, by the first device, second scheduling information including second indication information to a second device in a second time domain position, wherein the second indication information is used to indicate a second interval, which is the difference between the first interval and a third interval. The second scheduling information is used by the second device to determine that-the target time domain position used by the second device to determine a time domain resource used to send and/or receive data.

Abstract: Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.

Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Abstract: Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.

Abstract: An embodiment method includes: obtaining, by a communications device, a DRX period of a first device and an identifier of the first device; determining, according to the DRX period of the first device and the identifier of the first device, a paging occasion on which the first device pages a second device; and transmitting, by the communications device, a first paging message on the paging occasion on which the first device pages the second device, where the first paging message is used by the first device to page the second device, and the communications device is the first device or the second device.

Abstract: A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

Abstract: The present application provides a touch sensor and a fabricating method thereof and a touch display panel, comprising: a substrate, where the substrate includes a plurality of grooves which are strip-shaped and intersected with each other to define a grid shape; a first infiltrating adjustment layer, disposed on an inside wall of the grooves; and a touch electrodes filled in the groove. The first infiltrating adjustment layer is positioned between the groove and the touch electrodes. An infiltration angle between the touch electrodes in solution state and the first infiltrating adjustment layer is ?, an infiltration angle between the touch electrodes in solution state and the substrate is ?, wherein ? is not equal to ?.

Abstract: A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.

Abstract: A method of performing a random access procedure includes randomly selecting a backoff time from within a backoff window ranging from 0 to a specified multiple of a random access preamble unit, waiting until a time initialized with the backoff time expires, and retransmitting a random access preamble.

Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.

Abstract: Embodiments of the present invention provide an uplink subcarrier spacing indication method, a base station, and a terminal. The base station determines indication information that is used to indicate a first uplink subcarrier spacing supported by the base station, and communicates with the terminal according to the indication information. During the communication, the base station indicates the first uplink subcarrier spacing supported by the base station to the terminal, so that the terminal subsequently determines, based on the first uplink subcarrier spacing, a second uplink subcarrier spacing supported by the terminal; or the base station receives information that is sent by the terminal and that carries a second uplink subcarrier spacing, in other words, receives an indication from the terminal, so as to learn of the second uplink subcarrier spacing supported by the terminal or to be used by the terminal to send an uplink signal.

Abstract: A method is provided for controlling a storage system, which can include a plurality of memory cells arranged in blocks and a memory controller coupled to the plurality of memory cells for controlling data write and read in the plurality of memory cells. The method includes identifying a block as a good block, if a count of bad pages in the block is zero, identifying the block as a degraded block if the count of bad pages is below a threshold number, and identifying the block as a bad block if the count of bad pages is above or equal to the threshold number. The method includes using good blocks and degraded blocks for read and program operations, and not using the bad blocks.