Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A behavior analysis system, comprising: a first electronic device configured to capture image data of a scene to obtain a first monitoring message; a computing unit, in communication with the first electronic device, comprising: an artificial intelligence module configured to receive the first monitoring message and detect a first behavior event from the first monitoring message; an event aggregation module configured to aggregate the first behavior event to generate an event aggregation report; and a language model configured to generate a behavior summary based on the event aggregation report; and a user equipment, in communication with the first electronic device and the computing unit, configured to display the behavior summary; wherein the behavior summary is in a form of natural language.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: The present disclosure provides systems, apparatus, methods, and computer-readable media that support adapting image processing based on the user activity performed while recording an image. In a first aspect, a method of image processing may include determining a type of activity based on sensor data, such as motion sensors and/or image sensor data. The type of activity may be provided to an image processing algorithm, such as an image/video stabilization algorithm, which adapts based on the activity type. For example, a rolling shutter correction may have a strength factor that is adapted to lower values when the type of activity is a panning motion when faces are present in the frame. As another example, another image stabilization (IS) algorithm such as an electronic image stabilization (EIS) algorithm may have adaptive behavior adjusted based on the type of activity. Other aspects and features are also claimed and described.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: A hydrocarbon resin polymer is provided. The hydrocarbon resin polymer includes: 0.15-15 mol % of repeating units (A), which are derived from bridged ring monomer compounds; 15-90 mol % of repeating units (B), which are derived from monovinyl aromatic compounds; and 8-80 mol % of repeating units (C), which are derived from divinyl aromatic compounds.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: In general, techniques are described regarding fusing or combining frames of image data to generate composite frames of image data. Cameras comprising camera processors configured to perform the techniques are also disclosed. A camera processor may capture multiple frames at various focal lengths. The frames of image data may have various regions of the respective frame in focus, whereas other regions of the respective frame may not be in focus, due to particular configurations of lens and sensor combinations used. The camera processor may combine the frames to achieve a single composite frame having both a first region (e.g., a center region) and a second region (e.g., an outer region) in focus.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

Abstract: A probe module includes a circuit board and at least one probe formed on a probe installation surface of the circuit board by a microelectromechanical manufacturing process and including a probe body and a probe tip. The probe body includes first and second end portions and a longitudinal portion having first and second surfaces facing toward opposite first and second directions. The probe tip extends from the probe body toward the first direction and is processed with a gradually narrowing shape by laser cutting. The first and/or second end portion has a supporting seat protruding from the second surface toward the second direction and connected to the probe installation surface, such that the longitudinal portion and the probe tip are suspended above the probe installation surface. The probe has a tiny pinpoint for detecting tiny electronic components, and its manufacturing method is time-saving and high in yield rate.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: Techniques and systems are provided for processing image data. A first image having a first resolution can be obtained. In some aspects, the first image is generated based on a pixel binning process. A second image can be obtained having a second resolution that is greater than the first resolution. In some aspects, the second image is generated based on a remosaicing process. One or more weight maps can be generated based on characteristics determined based on pixels of the first image, pixels of the second image, or pixels of both the first image and the second image. A fused image can be generated based on the one or more weight maps that includes a first set of pixels from the first image and a second set of pixels from the second image.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.